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AgeCommit message (Collapse)Author
2011-06-19inorder: register ports for FS modeKorey Sewell
handle "snoop" port registration as well as functional port setup for FS mode
2011-06-19inorder: check for interrupts each tickKorey Sewell
use a dummy instruction to facilitate the squash after the interrupts trap
2011-06-19inorder: explicit fault checkKorey Sewell
Before graduating an instruction, explicitly check fault by making the fault check it's own separate command that can be put on an instruction schedule.
2011-06-19inorder: squash and trap behind a tlb faultKorey Sewell
2011-06-19inorder: stall stores on store conditionals & compare/swapsKorey Sewell
2011-06-19inorder: make InOrder CPU FS compilable/visibleKorey Sewell
make syscall a SE mode only functionality copy over basic FS functions (hwrei) to make FS compile
2011-06-19inorder: remove memdep tracking for default pipelineKorey Sewell
speculative load/store pipelines can reenable this
2011-06-19inorder: fetchBuffer trackingKorey Sewell
calculate blocks in use for the fetch buffer to figure out how many total blocks are pending
2011-06-19inorder: redefine DynInst FP result typeKorey Sewell
Sharing the FP value w/the integer values was giving inconsistent results esp. when their is a 32-bit integer register matched w/a 64-bit float value
2011-06-19inorder: treat SE mode syscalls as a trapping instructionKorey Sewell
define a syscallContext to schedule the syscall and then use syscall() to actually perform the action
2011-06-19inorder: bug in mduKorey Sewell
segfault was caused by squashed multiply thats in the process of an event. use isProcessing flag to handle this and cleanup the MDU code
2011-06-19inorder: optionally track faulting instructionsKorey Sewell
2011-06-19inorder: cleanup events in resource poolKorey Sewell
remove events in the resource pool that can be called from the CPU event, since the CPU event is scheduled at the same time at the resource pool event. ---- Also, match the resPool event function names to the cpu event function names ----
2011-06-19inorder: don't stall after storesKorey Sewell
once a ST is sent off, it's OK to keep processing, however it's a little more complicated to handle the packet acknowledging the store is completed
2011-06-19inorder: don't stall after storesKorey Sewell
once a ST is sent off, it's OK to keep processing, however it's a little more complicated to handle the packet acknowledging the store is completed
2011-06-19inorder: remove decode squashKorey Sewell
also, cleanup comments for gem5.fast compilation
2011-06-19inorder: support for compare and swap instsKorey Sewell
dont treat read() and write() fields as mut. exclusive
2011-06-19inorder: branch predictor updateKorey Sewell
only update BTB on a taken branch and update branch predictor w/pcstate from instruction --- only pay attention to branch predictor updates if the the inst. is in fact a branch
2011-06-19inorder: priority for grad/squash eventsKorey Sewell
define separate priority resource pool squash and graduate events
2011-06-19inorder: remove stalls on trap squashKorey Sewell
2011-06-19inorder: no dep. tracking for zero regKorey Sewell
this causes forwarding a bad value register value
2011-06-19imported patch recoverPCfromTrapKorey Sewell
2011-06-19imported patch squash_from_next_stageKorey Sewell
2011-06-19inorder: add flatDestReg member to dyninstKorey Sewell
use it in reg. dep. tracking
2011-06-19inorder: update event prioritiesKorey Sewell
dont use offset to calculate this but rather an enum that can be updated
2011-06-19inorder: implement trap handlingKorey Sewell
2011-06-19inorder: cleanup intercomm. structs/squash infoKorey Sewell
2011-06-19inorder: use setupSquash for misspeculationKorey Sewell
implement a clean interface to handle branch misprediction and eventually all pipeline flushing
2011-06-19inorder: DynInst handling of stores for big-endian ISAsKorey Sewell
The DynInst was not performing the host-to-guest translation which ended up breaking stores for SPARC
2011-06-19inorder: make marking of dest. regs an explicit requestKorey Sewell
formerly, this was implicit when you accessed the execution unit or the use-def unit but it's better that this just be something that a user can specify.
2011-06-19inorder: simplify handling of split accessesKorey Sewell
2011-06-19inorder: addtl functionaly for inst. skedsKorey Sewell
add find and end functions for inst. schedules that can search by stage number
2011-06-19inorder: register file statsKorey Sewell
keep stats for int/float reg file usage instead of aggregating across reg file types
2011-06-19inorder: scheduling for nonspec instsKorey Sewell
make handling of speculative and nonspeculative insts more explicit
2011-06-19inorder: find register dependencies "lazily"Korey Sewell
Architectures like SPARC need to read the window pointer in order to figure out it's register dependence. However, this may not get updated until after an instruction gets executed, so now we lazily detect the register dependence in the EXE stage (execution unit or use_def). This makes sure we get the mapping after the most current change.
2011-06-19inorder: assert on macro-opsKorey Sewell
provide a sanity check for someone coding a new architecture
2011-06-19inorder: handle faults at writeback stageKorey Sewell
call trap function when a fault is received
2011-06-19inorder: ISA-zero reg handlingKorey Sewell
ignore writes to the ISA zero register
2011-06-19inorder: update support for branch delay slotsKorey Sewell
2011-06-19inorder: inst. iterator cleanupKorey Sewell
get rid of accessing iterators (for instructions) by reference
2011-06-19inorder: update bpred codeKorey Sewell
clean up control flow to make it easier to understand
2011-06-19inorder: add types for dependency checksKorey Sewell
2011-06-19inorder: use flattenIdx for reg indexingKorey Sewell
- also use "threadId()" instead of readTid() everywhere - this will help support more complex ISA indexing
2011-06-19inorder: use m5_hash_map for skedCacheKorey Sewell
since we dont care about if the cache of instruction schedules is sorted or not, then the hash map should be faster
2011-06-09sparc: compilation fixes for inorderKorey Sewell
Add a few constants and functions that the InOrder model wants for SPARC. * * * sparc: add eaComp function InOrder separates the address generation from the actual access so give Sparc that functionality * * * sparc: add control flags for branches branch predictors and other cpu model functions need to know specific information about branches, so add the necessary flags here
2011-06-07gcc 4.0: Add some virtual destructors to make gcc 4.0 happy.Gabe Black
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-05-09work around gcc 4.5 warningNathan Binkert
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help