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use it in reg. dep. tracking
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dont use offset to calculate this but rather an enum
that can be updated
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implement a clean interface to handle branch misprediction and eventually all pipeline
flushing
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The DynInst was not performing the host-to-guest translation
which ended up breaking stores for SPARC
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formerly, this was implicit when you accessed the execution unit
or the use-def unit but it's better that this just be something
that a user can specify.
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add find and end functions for inst. schedules
that can search by stage number
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keep stats for int/float reg file usage instead
of aggregating across reg file types
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make handling of speculative and nonspeculative insts
more explicit
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Architectures like SPARC need to read the window pointer
in order to figure out it's register dependence. However,
this may not get updated until after an instruction gets
executed, so now we lazily detect the register dependence
in the EXE stage (execution unit or use_def). This
makes sure we get the mapping after the most current change.
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provide a sanity check for someone coding
a new architecture
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call trap function when a fault is received
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ignore writes to the ISA zero register
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get rid of accessing iterators (for instructions) by reference
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clean up control flow to make it easier to understand
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- also use "threadId()" instead of readTid() everywhere
- this will help support more complex ISA indexing
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since we dont care about if the cache of instruction schedules is sorted or not,
then the hash map should be faster
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Add a few constants and functions that the InOrder model wants for SPARC.
* * *
sparc: add eaComp function
InOrder separates the address generation from the actual access so give
Sparc that functionality
* * *
sparc: add control flags for branches
branch predictors and other cpu model functions need to know specific information
about branches, so add the necessary flags here
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At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
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***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
anyway.
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Because int and not InstSeqNum was used in a couple of places, you can
overflow the int type and thus get wierd bugs when the sequence number
is negative (or some wierd value)
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remove constructors that werent being used (it just gets confusing)
use initialization list for all the variables instead of relying on initVars()
function
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-use a pointer to CacheReqPacket instead of PacketPtr so correct destructors
get called on packet deletion
- make sure to delete the packet if the cache blocks the sendTiming request
or for some reason we dont use the packet
- dont overwrite memory requests since in the worst case an instruction will
be replaying a request so no need to keep allocating a new request
- we dont use retryPkt so delete it
- fetch code was split out already, so just assert that this is a memory
reference inst. and that the staticInst is available
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make sure instructions are able to commit before writing back to the RF
do not commit more than 1 non-speculative instruction per cycle
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keep track of when an instruction needs the execution
behind it to be serialized. Without this, in SE Mode
instructions can execute behind a system call exit().
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a lot of structures get allocated based off that MaxThreads parameter so this is an
effort to not abuse it
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resources don't need to call getLatency because the latency is already a member
in the class. If there is some type of special case where different instructions
impose a different latency inside a resource then we can revisit this and
add getLatency() back in
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each resource has a certain # of requests it can take per cycle. update the #s here
to be more realistic based off of the pipeline width and if the resource needs to
be accessed on multiple cycles
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cleanup hanging pointers and other cruft in the destructors
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---
need to delete the cache request's data on clearRequest() now that we are recycling
requests
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fetch unit needs to deallocate the fetch buffer blocks when they are replaced or
squashed.
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if a resource has a zero cycle latency (e.g. RegFile write), then dont allocate an event
for it to use
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formerly, to free up bandwidth in a resource, we could just change the pointer in that resource
but at the same time the pipeline stages had visibility to see what happened to a resource request.
Now that we are recycling these requests (to avoid too much dynamic allocation), we can't throw
away the request too early or the pipeline stage gets bad information. Instead, mark when a request
is done with the resource all together and then let the pipeline stage call back to the resource
that it's time to free up the bandwidth for more instructions
*** inteface notes ***
- When an instruction completes and is done in a resource for that cycle, call done()
- When an instruction fails and is done with a resource for that cycle, call done(false)
- When an instruction completes, but isnt finished with a resource, call completed()
- When an instruction fails, but isnt finished with a resource, call completed(false)
* * *
inorder: tlbmiss wakeup bug fix
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take away all instances of reqMap in the code and make all references use the built-in
request vectors inside of each resource. The request map was dynamically allocating
a request per instruction. The request vector just allocates N number of requests
during instantiation and then the surrounding code is fixed up to reuse those N requests
***
setRequest() and clearRequest() are the new accessors needed to define a new
request in a resource
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this will allow us to reuse resource requests within a resource instead
of always dynamically allocating
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we are going to be getting away from creating new resource requests for every
instruction so no more need to keep track of a reqRemoveList and clean it up
every tick
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first change in an optimization that will stop InOrder from allocating new memory for every instruction's
request to a resource. This gets expensive since every instruction needs to access ~10 requests before
graduation. Instead, the plan is to allocate just enough resource request objects to satisfy each resource's
bandwidth (e.g. the execution unit would need to allocate 3 resource request objects for a 1-issue pipeline
since on any given cycle it could have 2 read requests and 1 write request) and then let the instructions
contend and reuse those allocated requests. The end result is a smaller memory footprint for the InOrder model
and increased simulation performance
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remove remnants of old way of instruction scheduling which dynamically allocated
a new resource schedule for every instruction
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allow the pipeline and resources to use the cached instruction schedule and resource
sked iterator
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