| Age | Commit message (Expand) | Author |
|---|
| 2013-09-04 | cpu: Move the branch predictor out of the BaseCPU | Andreas Hansson |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-04-22 | sim: separate nextCycle() and clockEdge() in clockedObjects | Dam Sunwoo |
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-03-20 | cpu: Avoid including inorder TLBUnit to avoid gcc LTO bug | Andreas Hansson |
| 2013-02-15 | sim: Add a system-global option to bypass caches | Andreas Sandberg |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-02-15 | cpu: Add CPU metadata om the Python classes | Andreas Sandberg |
| 2013-01-24 | branch predictor: move out of o3 and inorder cpus | Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E) |
| 2013-01-07 | cpu: Fix broken thread context handover | Andreas Sandberg |
| 2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
| 2013-01-07 | cpu: Remove unused params.hh header file in inorder CPU | Andreas Sandberg |
| 2013-01-07 | cpu: Unify SimpleCPU and O3 CPU serialization code | Andreas Sandberg |
| 2013-01-07 | cpu: Implement a flat register interface in thread contexts | Andreas Sandberg |
| 2013-01-07 | cpu: Check that the memory system is in the correct mode | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
| 2013-01-07 | cpu: rename the misleading inSyscall to noSquashFromTC | Ali Saidi |
| 2013-01-04 | Decoder: Remove the thread context get/set from the decoder. | Gabe Black |
| 2012-12-06 | TournamentBP: Fix some bugs with table sizes and counters | Erik Tomusk |
| 2012-12-06 | inorder cpu: add missing DPRINTF argument | Malek Musleh |
| 2012-11-02 | sim: Include object header files in SWIG interfaces | Andreas Sandberg |
| 2012-09-07 | Param: Transition to Cycles for relevant parameters | Andreas Hansson |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
| 2012-08-21 | CPU: Remove overloaded function_trace_start parameter | Andreas Hansson |
| 2012-08-06 | process: add progName() virtual function | Steve Reinhardt |
| 2012-07-09 | Port: Align port names in C++ and Python | Andreas Hansson |
| 2012-06-05 | cpu: Don't init simple and inorder CPUs if they are defered. | Anthony Gutierrez |
| 2012-06-05 | sim: Remove FastAlloc | Ali Saidi |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Remove the Broadcast destination from the packet | Andreas Hansson |
| 2012-04-14 | MEM: Separate snoops and normal memory requests/responses | Andreas Hansson |
| 2012-04-14 | clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 | Andreas Hansson |
| 2012-04-06 | MEM: Enable multiple distributed generalized memories | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-30 | CPU: Unify initMemProxies across CPUs and simulation modes | Andreas Hansson |
| 2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
| 2012-03-09 | CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU | Geoffrey Blake |
| 2012-03-02 | DynInst: get rid of dead MyHash code. | Steve Reinhardt |
| 2012-03-02 | CPU: Check that the interrupt controller is created when needed | Andreas Hansson |
| 2012-02-24 | MEM: Make port proxies use references rather than pointers | Andreas Hansson |
| 2012-02-24 | CPU: Round-two unifying instr/data CPU ports across models | Andreas Hansson |
| 2012-02-13 | BP: Fix several Branch Predictor issues. | Mrinmoy Ghosh |
| 2012-02-12 | cpu: add separate stats for insts/ops both globally and per cpu model | Anthony Gutierrez |
| 2012-02-12 | mem: Add a master ID to each request object. | Ali Saidi |
| 2012-02-07 | Faults: Turn off arch/faults.hh | Gabe Black |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | clang: Enable compiling gem5 using clang 2.9 and 3.0 | Koan-Sin Tan |
