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path: root/src/cpu/minor/lsq.cc
AgeCommit message (Expand)Author
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2015-07-19cpu: Fix LLSC atomic CPU wakeupKrishnendra Nathella
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-08-21mem: Reflect that packet address and size are always validAndreas Hansson
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-01-25sim: Clean up InstRecordAli Saidi
2015-01-20cpu: Fix retry bug in MinorCPU LSQAndreas Hansson
2015-01-03minor: fixed LSQ MasterPortIDAndrew Lukefahr
2014-12-02cpu: Fix retries on barrier/store in Minor's store bufferAndrew Bardsley
2014-12-02mem: Assume all dynamic packet data is array allocatedAndreas Hansson
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-10-29cpu: Fix barrier push to store buffer when full bug in MinorAndrew Bardsley
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-12cpu: Fix memory access in Minor not setting parent Request flagsAndrew Bardsley
2014-07-23cpu: `Minor' in-order CPU modelAndrew Bardsley