gem5 - gem5

Age	Commit message (Expand)	Author
2015-05-26	cpu: Fix a bug in counting issued instructions in MinorCPU	Andrew Bardsley
2015-05-05	mem, cpu: Add a separate flag for strictly ordered memory	Andreas Sandberg
2015-05-05	cpu: Work around gcc 4.9 issues with Num_OpClasses	Andreas Hansson
2015-04-13	cpu: re-organizes the branch predictor structure.	Dibakar Gope
2015-04-03	cpu: fix system total instructions accounting	Nikos Nikoleris
2015-02-11	mem: restructure Packet cmd initialization a bit more	Steve Reinhardt
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2015-01-25	sim: Clean up InstRecord	Ali Saidi
2015-01-20	cpu: Fix retry bug in MinorCPU LSQ	Andreas Hansson
2015-01-03	minor: fixed LSQ MasterPortID	Andrew Lukefahr
2014-12-02	cpu: Fix retries on barrier/store in Minor's store buffer	Andrew Bardsley
2014-12-02	cpu: Fix memoryIssueLimit checking in Minor	Andrew Bardsley
2014-12-02	mem: Assume all dynamic packet data is array allocated	Andreas Hansson
2014-12-02	mem: Add const getters for write packet data	Andreas Hansson
2014-11-14	arm: Fixes based on UBSan and static analysis	Andreas Hansson
2014-11-06	x86 isa: This patch attempts an implementation at mwait.	Marc Orr
2014-11-06	cpu: Minor Draining Bug	Andrew Lukefahr
2014-10-29	cpu: Fix barrier push to store buffer when full bug in Minor	Andrew Bardsley
2014-10-16	cpu: Probe points for basic PMU stats	Andreas Sandberg
2014-09-27	arch: Use const StaticInstPtr references where possible	Andreas Hansson
2014-09-20	alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate	Mitch Hayenga
2014-09-19	arch: Pass faults by const reference where possible	Andreas Hansson
2014-09-12	cpu: Fix memory access in Minor not setting parent Request flags	Andrew Bardsley
2014-09-12	minor: Fix typo in DPRINTF for Minor branch prediction	Andreas Hansson
2014-09-03	arch, cpu: Factor out the ExecContext into a proper base class	Andreas Sandberg
2014-07-23	cpu: `Minor' in-order CPU model	Andrew Bardsley