index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
nativetrace.cc
Age
Commit message (
Expand
)
Author
2016-11-09
style: [patch 1/22] use /r/3648/ to reorganize includes
Brandon Potter
2016-02-06
style: fix missing spaces in control statements
Steve Reinhardt
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-01-03
Make commenting on close namespace brackets consistent.
Steve Reinhardt
2009-07-27
ARM: Make native trace print out what instruction caused an error.
Gabe Black
2009-07-19
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
Gabe Black
2009-07-08
Registers: Add a registers.hh file as an ISA switched header.
Gabe Black
2008-08-03
sockets: Add a function to disable all listening sockets.
Nathan Binkert
2007-09-04
X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actua...
Gabe Black
2007-08-31
X86: Get x86 to compile again after the simobject constructor change.
Gabe Black
2007-08-01
X86: Reorganize the native tracing code.
Gabe Black
2007-07-29
X86: Fix register ordering.
Gabe Black
2007-07-28
Turn the instruction tracing code into pluggable sim objects.
Gabe Black