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:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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path:
root
/
src
/
cpu
/
nativetrace.hh
Age
Commit message (
Expand
)
Author
2016-02-06
style: fix missing spaces in control statements
Steve Reinhardt
2015-01-25
cpu: Remove all notion that we know when the cpu is misspeculating.
Ali Saidi
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2011-04-15
includes: sort all includes
Nathan Binkert
2011-01-03
Make commenting on close namespace brackets consistent.
Steve Reinhardt
2010-10-31
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
Gabe Black
2009-07-27
ARM: Make native trace print out what instruction caused an error.
Gabe Black
2009-07-19
CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
Gabe Black
2009-05-17
includes: sort includes again
Nathan Binkert
2009-05-17
types: Move stuff for global types into src/base/types.hh
Nathan Binkert
2009-01-06
Tracing: Make tracing aware of macro and micro ops.
Gabe Black
2007-09-04
X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actua...
Gabe Black
2007-08-31
X86: Get x86 to compile again after the simobject constructor change.
Gabe Black
2007-08-01
X86: Reorganize the native tracing code.
Gabe Black
2007-07-28
Turn the instruction tracing code into pluggable sim objects.
Gabe Black