gem5 - gem5

Age	Commit message (Collapse)	Author
2009-07-27	ARM: Make native trace print out what instruction caused an error.	Gabe Black

2009-07-19	CPU: Separate out native trace into ISA (in)dependent code and SimObjects.	Gabe Black
	--HG-- rename : src/cpu/nativetrace.cc => src/arch/sparc/nativetrace.cc rename : src/cpu/nativetrace.hh => src/arch/sparc/nativetrace.hh rename : src/cpu/NativeTrace.py => src/arch/x86/X86NativeTrace.py
2009-05-17	includes: sort includes again	Nathan Binkert

2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
	--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-01-06	Tracing: Make tracing aware of macro and micro ops.	Gabe Black

2007-09-04	X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and ↵	Gabe Black
	actually compare xmm. --HG-- extra : convert_revision : 02c6641200edb133c9bc11f1fdf3c1a0b1c87e77
2007-08-31	X86: Get x86 to compile again after the simobject constructor change.	Gabe Black
	--HG-- extra : convert_revision : 17a3e16e849bee88892223f0c993b19c15daa554
2007-08-01	X86: Reorganize the native tracing code.	Gabe Black
	Ignore different values or rcx and r11 after a syscall until either the local or remote value changes. Also change the codes organization somewhat. --HG-- extra : convert_revision : 2c1f69d4e55b443e68bfc7b43e8387b02cf0b6b5
2007-07-28	Turn the instruction tracing code into pluggable sim objects.	Gabe Black
	These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7