| Age | Commit message (Expand) | Author |
|---|
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2016-10-15 | cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass | Fernando Endo |
| 2015-04-29 | cpu: o3: replace issueLatency with bool pipelined | Nilay Vaish |
| 2015-04-29 | cpu: o3: single cycle default div microop latency on x86 | Nilay Vaish |
| 2010-11-15 | CPU/ARM: Add SIMD op classes to CPU models and ARM ISA. | Giacomo Gabrielli |
| 2007-05-27 | Move SimObject python files alongside the C++ and fix | Nathan Binkert |
