gem5 - gem5

Age	Commit message (Expand)	Author
2014-04-29	arm: use condition code registers for ARM ISA	Curtis Dunham
2014-09-03	cpu: Fix SMT scheduling issue with the O3 cpu	Mitch Hayenga
2014-09-03	cpu: Add a fetch queue to the o3 cpu	Mitch Hayenga
2014-09-03	cpu: Change writeback modeling for outstanding instructions	Mitch Hayenga
2013-11-15	cpu: allow the fetch buffer to be smaller than a cache line	Anthony Gutierrez
2013-10-15	arch/x86: add support for explicit CC register file	Yasuko Eckert
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-09-04	cpu: Move the branch predictor out of the BaseCPU	Andreas Hansson
2013-02-15	cpu: Add CPU metadata om the Python classes	Andreas Sandberg
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2012-11-02	cpu: O3 add a header declaring the DerivO3CPU	Andreas Sandberg
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-07-27	checker: make checker cpu id match its host's cpu id	Anthony Gutierrez
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-28	O3 CPU LSQ: Implement TSO	Nilay Vaish
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-07	Merge with the main repository again.	Gabe Black
2011-12-01	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	Chander Sudanthi
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-08-19	LSQ: Set store predictor to periodically clear itself as recommended in the s...	Ali Saidi
2011-04-04	O3: Tighten memory order violation checking to 16 bytes.	Ali Saidi
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2007-11-12	X86: Implement a page table walker.	Gabe Black
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-06-20	Make sure all parameters have default values if they're	Nathan Binkert
2007-05-27	Move SimObject python files alongside the C++ and fix	Nathan Binkert