| Age | Commit message (Expand) | Author |
|---|---|---|
| 2011-12-01 | O3: Remove hardcoded tgts_per_mshr in O3CPU.py. | Chander Sudanthi |
| 2011-08-19 | LSQ: Set store predictor to periodically clear itself as recommended in the s... | Ali Saidi |
| 2011-04-04 | O3: Tighten memory order violation checking to 16 bytes. | Ali Saidi |
| 2011-02-03 | Config: Keep track of uncached and cached ports separately. | Gabe Black |
| 2011-02-01 | X86: Add L1 caches for the TLB walkers. | Gabe Black |
| 2009-09-22 | python: Move more code into m5.util allow SCons to use that code. | Nathan Binkert |
| 2008-08-11 | params: Convert the CPU objects to use the auto generated param structs. | Nathan Binkert |
| 2007-11-12 | X86: Implement a page table walker. | Gabe Black |
| 2007-08-26 | Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. | Gabe Black |
| 2007-06-20 | Make sure all parameters have default values if they're | Nathan Binkert |
| 2007-05-27 | Move SimObject python files alongside the C++ and fix | Nathan Binkert |
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