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path: root/src/cpu/o3/O3CPU.py
AgeCommit message (Expand)Author
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-10-15arch/x86: add support for explicit CC register fileYasuko Eckert
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-09-04cpu: Move the branch predictor out of the BaseCPUAndreas Hansson
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-07-27checker: make checker cpu id match its host's cpu idAnthony Gutierrez
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-29Yet another merge with the main repository.Gabe Black
2012-01-28O3 CPU LSQ: Implement TSONilay Vaish
2012-01-28Merge with the main repo.Gabe Black
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-07Merge with the main repository again.Gabe Black
2011-12-01O3: Remove hardcoded tgts_per_mshr in O3CPU.py.Chander Sudanthi
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-08-19LSQ: Set store predictor to periodically clear itself as recommended in the s...Ali Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2007-11-12X86: Implement a page table walker.Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-06-20Make sure all parameters have default values if they'reNathan Binkert
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert