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path: root/src/cpu/o3/O3CPU.py
AgeCommit message (Expand)Author
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2007-11-12X86: Implement a page table walker.Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-06-20Make sure all parameters have default values if they'reNathan Binkert
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert