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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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path:
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src
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cpu
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o3
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alpha
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cpu_builder.cc
Age
Commit message (
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Author
2007-10-02
CPU: Make sure the system parameter gets set in the cpu builders. Other param...
Gabe Black
2007-08-26
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
Gabe Black
2007-07-30
Fix problem with tracer not being initialized.
Gabe Black
2007-07-23
Major changes to how SimObjects are created and initialized. Almost all
Nathan Binkert
2007-03-23
A couple of minor fixes.
Kevin Lim
2006-11-14
Make cpu's capable of having a phase shift
Ron Dreslinski
2006-11-11
Get rid of the ParamContext for pseudo instructions and move
Nathan Binkert
2006-11-01
Merge zizzer.eecs.umich.edu:/bk/newmem/
Gabe Black
2006-11-01
Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...
Gabe Black
2006-10-31
Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...
Kevin Lim
2006-10-02
Updates to fix merge issues and bring almost everything up to working speed. ...
Kevin Lim
2006-09-30
Merge ktlim@zamp:./local/clean/o3-merge/m5
Kevin Lim
2006-07-10
Add parameters for backwards and forwards sizes for time buffers.
Kevin Lim
2006-07-05
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-02
typo ... change 'single_thread' to 'round_robin_policy'
Korey Sewell
2006-07-02
Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Korey Sewell
2006-07-01
fix cpu builder to build the correct name...
Korey Sewell
2006-06-30
Make O3CPU model independent of the ISA
Korey Sewell