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path: root/src/cpu/o3/alpha
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2007-01-27Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/system.cc: Hand Merge --HG-- extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
2007-01-26eliminate cpu checkInterrupts bool, it is redundant and unnecessary.Lisa Hsu
--HG-- extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
2006-12-28Implement a stub nnpc for alpha that is read only as npc+4.Gabe Black
--HG-- extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-20Fixes to get ALPHA_FS and ALPHA_SE to compile again.Gabe Black
--HG-- extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-17Convert Alpha (and finish converting MIPS) to newSteve Reinhardt
InstObjParam interface. src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/fp.isa: src/arch/alpha/isa/int.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/isa/mem.isa: src/arch/alpha/isa/pal.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/util.isa: Get rid of CodeBlock calls to adapt to new InstObjParam interface. src/arch/isa_parser.py: Check template code for operands (in addition to snippets). src/cpu/o3/alpha/dyn_inst.hh: Add (read|write)MiscRegOperand calls to Alpha DynInst. --HG-- extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
2006-12-12Rename the StaticInst-based (read|set)(Int|Float)Reg methods to ↵Steve Reinhardt
(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. --HG-- extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-06Moved the RegIdx arrays to the base dyninst.Gabe Black
--HG-- extra : convert_revision : d705cde25c2cf1add20669e99d086add49141518
2006-12-06Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the ↵Gabe Black
architecture defined setSyscallReturn function instead of a duplicate copy. src/cpu/o3/alpha/cpu.hh: Got rid of some typedefs, and moved the tlbs to the base o3 cpu. src/cpu/o3/alpha/thread_context.hh: src/cpu/o3/cpu.cc: Moved the tlbs to the base o3 cpu. --HG-- extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
2006-11-19Update Virtual and Physical ports.Kevin Lim
src/cpu/o3/alpha/cpu_impl.hh: Handle the PhysicalPort and VirtualPort in the ThreadState. src/cpu/o3/cpu.cc: Initialize the thread context. src/cpu/o3/thread_context.hh: Add new function to initialize thread context. src/cpu/o3/thread_context_impl.hh: Use code now put into function. src/cpu/simple_thread.cc: Move code to ThreadState and use the new helper function. src/cpu/simple_thread.hh: Remove init() in this derived class; use init() from ThreadState base class. src/cpu/thread_state.cc: Move setting up of Physical and Virtual ports here. Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU. src/cpu/thread_state.hh: Update functions. --HG-- extra : convert_revision : ff254715ef0b259dc80d08f13543b63e4024ca8d
2006-11-14Make cpu's capable of having a phase shiftRon Dreslinski
--HG-- extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
2006-11-12Merge ktlim@zamp:./local/clean/tmp/test-regressKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
2006-11-12Updates to support new interrupt processing and removal of PcPAL.Kevin Lim
src/arch/alpha/interrupts.hh: No need for this now that the ThreadContext is being used to set these IPRs in interrupts. Also split up the interrupt checking from the updating of the IPL and interrupt summary. src/arch/alpha/tlb.cc: Check the PC for whether or not it's in PAL mode, not the addr. src/cpu/o3/alpha/cpu.hh: Split up getting the interrupt from actually processing the interrupt. src/cpu/o3/alpha/cpu_impl.hh: Splut up the processing of interrupts. src/cpu/o3/commit_impl.hh: Update for ISA-oriented interrupt changes. src/cpu/o3/fetch_impl.hh: Fix broken if statement from PcPAL updates, and properly populate the request fields. Also more debugging output. src/cpu/ozone/cpu_impl.hh: Updates for ISA-oriented interrupt stuff. src/cpu/ozone/front_end_impl.hh: Populate request fields properly. src/cpu/simple/base.cc: Update for interrupt stuff. --HG-- extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
the parameters to the BaseCPU object. --HG-- extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
2006-11-11The Lock_Flag_DepTag went away earlier, and using TheISA gives the false ↵Gabe Black
impression that this code is ISA independent. --HG-- extra : convert_revision : 67d9e51702efbe5f5244268e3753328a6cf1a1d5
2006-11-10Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
2006-11-07Put kernel_stats back into arch.Gabe Black
--HG-- rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
2006-11-03Got rid of "inPalMode". Some places are still effectively checking if they ↵Gabe Black
are in PAL mode, however. --HG-- extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
2006-11-03Add a new file which describes an ISA's interrupt handling mechanism. It ↵Gabe Black
records when interrupts are requested, and returns an interrupt to execute if the --HG-- extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
2006-11-01Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops --HG-- extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
2006-11-01Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ↵Gabe Black
file functions to not take faults --HG-- extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ↵Kevin Lim
for its MemObject instead of having to have a paramter for the MemObject. configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter. --HG-- extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
2006-10-31Missed a few instances of this function.Gabe Black
--HG-- extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
2006-10-31Move IntrFlag into the MiscRegFile and get rid of specialized accessor ↵Gabe Black
functions. --HG-- extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
2006-10-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : 161c35ade82f2471e605d948dca56cfa216693fd
2006-10-23Add in support for LL/SC in the O3 CPU. Needs to be fully tested.Kevin Lim
src/cpu/base_dyn_inst.hh: Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code). src/cpu/base_dyn_inst_impl.hh: Add variable to track if the result of the instruction should be recorded. src/cpu/o3/alpha/cpu_impl.hh: Clear lock flag upon hwrei. src/cpu/o3/lsq_unit.hh: Use ISA specified handling of locked reads. src/cpu/o3/lsq_unit_impl.hh: Use ISA specified handling of locked writes. --HG-- extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
2006-10-20Use PacketPtr everywhereNathan Binkert
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ↵Kevin Lim
Ozone CPU remains untested, but everything else compiles and runs. src/arch/alpha/isa_traits.hh: This got changed to the wrong version by accident. src/cpu/base.cc: Fix up progress event to not schedule itself if the interval is set to 0. src/cpu/base.hh: Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here). src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: Remove float variable of instResult; it's always held within the double part now. src/cpu/checker/cpu_impl.hh: Use thread and not cpuXC. src/cpu/o3/alpha/cpu_builder.cc: src/cpu/o3/checker_builder.cc: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu_builder.cc: src/python/m5/objects/BaseCPU.py: Remove stats_reset_inst. src/cpu/o3/commit_impl.hh: src/cpu/ozone/lw_back_end_impl.hh: Get TC, not XCProxy. src/cpu/o3/cpu.cc: Switch out updates from the version of m5 I have. Also remove serialize code that got added twice. src/cpu/o3/iew_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/thread_state.hh: Remove code that was added twice. src/cpu/o3/lsq_unit.hh: Add back in stats that got lost in the merge. src/cpu/o3/lsq_unit_impl.hh: Use proper method to get flags. Also wake CPU if we're coming back from a cache miss. src/cpu/o3/thread_context_impl.hh: src/cpu/o3/thread_state.hh: Support profiling. src/cpu/ozone/cpu.hh: Update to use proper typename. src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst_impl.hh: Updates for newmem. src/cpu/ozone/lw_lsq_impl.hh: Get flags correctly. src/cpu/ozone/thread_state.hh: Reorder constructor initialization, use tc. src/sim/pseudo_inst.cc: Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext. --HG-- extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge. --HG-- rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/checker/cpu.hh => src/cpu/checker/cpu.hh rename : cpu/checker/cpu.cc => src/cpu/checker/cpu_impl.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : cpu/checker/o3_cpu_builder.cc => src/cpu/o3/checker_builder.cc rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/lsq_impl.hh => src/cpu/o3/lsq_impl.hh rename : cpu/o3/lsq_unit.hh => src/cpu/o3/lsq_unit.hh rename : cpu/o3/lsq_unit_impl.hh => src/cpu/o3/lsq_unit_impl.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/thread_state.hh => src/cpu/o3/thread_state.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/checker/cpu_builder.cc => src/cpu/ozone/checker_builder.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_builder.cc => src/cpu/ozone/cpu_builder.cc rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/front_end.hh => src/cpu/ozone/front_end.hh rename : cpu/ozone/front_end_impl.hh => src/cpu/ozone/front_end_impl.hh rename : cpu/ozone/inorder_back_end_impl.hh => src/cpu/ozone/inorder_back_end_impl.hh rename : cpu/ozone/inst_queue_impl.hh => src/cpu/ozone/inst_queue_impl.hh rename : cpu/ozone/lw_back_end.hh => src/cpu/ozone/lw_back_end.hh rename : cpu/ozone/lw_back_end_impl.hh => src/cpu/ozone/lw_back_end_impl.hh rename : cpu/ozone/lw_lsq.hh => src/cpu/ozone/lw_lsq.hh rename : cpu/ozone/lw_lsq_impl.hh => src/cpu/ozone/lw_lsq_impl.hh rename : cpu/ozone/simple_params.hh => src/cpu/ozone/simple_params.hh rename : cpu/ozone/thread_state.hh => src/cpu/ozone/thread_state.hh rename : cpu/simple/cpu.cc => src/cpu/simple/base.cc rename : cpu/cpu_exec_context.cc => src/cpu/simple_thread.cc rename : cpu/thread_state.hh => src/cpu/thread_state.hh rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/O3CPU.py rename : python/m5/objects/OzoneCPU.py => src/python/m5/objects/OzoneCPU.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/system.hh => src/sim/system.hh extra : convert_revision : 135d90e43f6cea89f9460ba4e23f4b0b85886e7d
2006-08-15Some touchup to the reorganized includes and "using" directives.Gabe Black
--HG-- extra : convert_revision : 956c80d6d826b08e52c0892a480a0a9b74b96b9d
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
--HG-- extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and ↵Gabe Black
created a seperate file for the syscallreturn class. --HG-- extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It ↵Korey Sewell
builds, runs, and gets very very close to completing the hello world succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh! Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... ) src/arch/alpha/isa/mem.isa: spacing src/arch/mips/faults.cc: src/arch/mips/faults.hh: Gabe really authored this src/arch/mips/isa/decoder.isa: add StoreConditional Flag to instruction src/arch/mips/isa/formats/basic.isa: Steven really did this file src/arch/mips/isa/formats/branch.isa: fix bug for uncond/cond control src/arch/mips/isa/formats/mem.isa: Adjust O3CPU memory access to use new memory model interface. src/arch/mips/isa/formats/util.isa: update LoadStoreBase template src/arch/mips/isa_traits.cc: update SERIALIZE partially src/arch/mips/process.cc: src/arch/mips/process.hh: no need for this for NOW. ASID/Virtual addressing handles it src/arch/mips/regfile/misc_regfile.hh: add in clear() function and comments for future usage of special misc. regs src/cpu/base_dyn_inst.hh: add in nextNPC variable and supporting functions. add isCondDelaySlot function Update predTaken and mispredicted functions src/cpu/base_dyn_inst_impl.hh: init nextNPC src/cpu/o3/SConscript: add MIPS files to compile src/cpu/o3/alpha/thread_context.hh: no need for my name on this file src/cpu/o3/bpred_unit_impl.hh: Update RAS appropriately for MIPS src/cpu/o3/comm.hh: add some extra communication variables to aid in handling the delay slots src/cpu/o3/commit.hh: minor name fix for nextNPC functions. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rename_impl.hh: Fix necessary variables and functions for squashes with delay slots src/cpu/o3/cpu.cc: Update function interface ... adjust removeInstsNotInROB function to recognize delay slots insts src/cpu/o3/cpu.hh: update removeInstsNotInROB src/cpu/o3/decode.hh: declare necessary variables for handling delay slot src/cpu/o3/dyn_inst.hh: Add in MipsDynInst src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/rename.hh: declare necessary variables and adjust functions for handling delay slot src/cpu/o3/inst_queue.hh: src/cpu/simple/base.cc: no need for my name here src/cpu/o3/isa_specific.hh: add in MIPS files src/cpu/o3/scoreboard.hh: dont include alpha specific isa traits! src/cpu/o3/thread_context.hh: no need for my name here, i just rearranged where the file goes src/cpu/static_inst.hh: add isCondDelaySlot function src/cpu/o3/mips/cpu.cc: src/cpu/o3/mips/cpu.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/mips/dyn_inst.cc: src/cpu/o3/mips/dyn_inst.hh: src/cpu/o3/mips/dyn_inst_impl.hh: src/cpu/o3/mips/impl.hh: src/cpu/o3/mips/params.hh: src/cpu/o3/mips/thread_context.cc: src/cpu/o3/mips/thread_context.hh: MIPS file for O3CPU...mirrors ALPHA definition --HG-- extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
2006-07-10Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge --HG-- extra : convert_revision : 0e4c7684879b8552908e0b64a00b4824de807244
2006-07-10Add parameters for backwards and forwards sizes for time buffers.Kevin Lim
src/base/timebuf.hh: Add a function to return the size of the time buffer. --HG-- extra : convert_revision : 8ffacd8b9013eb76264df065244e00dc1460efd4
2006-07-07Fix so that O3CPU doesnt segfault on exit.Korey Sewell
Major thing was to not execute commit if there are no active threads in CPU. src/cpu/o3/alpha/thread_context.hh: call deallocate instead of deallocateContext src/cpu/o3/commit_impl.hh: dont run commit stage if there are no instructions src/cpu/o3/cpu.cc: add deallocate event, deactivateThread function, and edit deallocateContext. src/cpu/o3/cpu.hh: add deallocate event and add optional delay to deallocateContext src/cpu/o3/thread_context.hh: optional delay for deallocate src/cpu/o3/thread_context_impl.hh: edit DPRINTFs to say Thread Context instead of Alpha TC src/cpu/thread_context.hh: optional delay src/sim/syscall_emul.hh: name stuff --HG-- extra : convert_revision : f4033e1f66b3043d30ad98dcc70d8b193dea70b6
2006-07-06Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3 --HG-- extra : convert_revision : 2f08ea52ef54118d42aa590c0d86aa0cc7988713
2006-07-06more steps toward O3 SMTKorey Sewell
src/arch/mips/isa/formats/fp.isa: Adjust for newmem src/cpu/cpu_models.py: Use O3DynInst instead of convoluted way src/cpu/o3/alpha/impl.hh: take out O3DynInst typedef here ... src/cpu/o3/cpu.cc: open up the SMT functions in the O3CPU src/cpu/static_inst.hh: Add O3DynInst src/cpu/o3/dyn_inst.hh: Use to get ISA-specific O3DynInst --HG-- extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
2006-07-05Fix up some merge problems.Kevin Lim
src/base/traceflags.py: Remove BaseCPU traceflag. src/cpu/o3/alpha/params.hh: Move non-Alpha specific parameters out of this params class. src/cpu/o3/params.hh: Move non-Alpha specific params into this params class. --HG-- extra : convert_revision : e5b652adb47a240376733400e6054c66c50bd514
2006-07-05Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge src/base/traceflags.py: src/cpu/SConscript: Hand merge. src/cpu/o3/alpha/params.hh: Hand merge. This needs to get changed. --HG-- rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : 581f338f5bce35288f7d15d95cbd0ac3a9135e6a
2006-07-03Fix for FS O3CPU compile ... missing forward class declaration/header file ↵Korey Sewell
after files got split for ISA-independence src/cpu/o3/alpha/thread_context.hh: Use 'this' when accessing cpu src/cpu/o3/cpu.hh: add numActiveThreds function src/cpu/o3/thread_context.hh: forward class declarations src/cpu/o3/thread_context_impl.hh: add quiesce event header file src/cpu/thread_context.hh: add exit() function to thread context (read comments in file) src/sim/syscall_emul.cc: adjust exitFunc syscall --HG-- extra : convert_revision : 323dc871e2b4f4ee5036be388ceb6634cd85a83e
2006-07-02typo ... change 'single_thread' to 'round_robin_policy'Korey Sewell
--HG-- extra : convert_revision : a4a5cb90557f786d42c6178bc6e268312c5ecbee
2006-07-02Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)Korey Sewell
Edit Test3 for newmem src/base/traceflags.py: Add O3CPU flag src/cpu/base.cc: for some reason adding a BaseCPU flag doesnt work so just go back to old way... src/cpu/o3/alpha/cpu_builder.cc: Determine number threads by workload size instead of solely by parameter. Default SMT fetch policy to RoundRobin if it's not specified in Config file src/cpu/o3/commit.hh: only use nextNPC for !ALPHA src/cpu/o3/commit_impl.hh: add FetchTrapPending as condition for commit src/cpu/o3/cpu.cc: panic if active threads is more than Impl::MaxThreads src/cpu/o3/fetch.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: name stuff src/cpu/o3/fetch_impl.hh: fatal if try to use SMT branch count, that's unimplemented right now src/python/m5/config.py: make it clearer that a parameter is not valid within a configuration class --HG-- extra : convert_revision : 55069847304e40e257f9225f0dc3894ce6491b34
2006-07-01fix cpu builder to build the correct name...Korey Sewell
add activateThread event and functions src/cpu/o3/alpha/cpu_builder.cc: Have CPU builder build a DerivO3CPU not a DerivAlphaO3CPU src/cpu/o3/cpu.cc: add activateThread Event add activateThread function adjust activateContext to schedule a thread to activate within the CPU instead of activating thread right away. This will lead to stages trying to use threads that arent ready yet and wasting execution time & possibly performance. src/cpu/o3/cpu.hh: add activateThread Event add activateThread function add schedule/descheculed activate thread event --HG-- extra : convert_revision : 236d30dc160910507ad36f7f527ab185ed38dc04
2006-06-30now O3CPU is totally independent of the ISA... all alpha specific stuff is ↵Korey Sewell
the cpu/o3/alpha directory src/cpu/o3/alpha/cpu.cc: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/impl.hh: filenames src/cpu/o3/alpha/thread_context.hh: public src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use O3CPUImpl ... not Alpha src/cpu/o3/checker_builder.cc: filename --HG-- extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69
2006-06-30Make O3CPU model independent of the ISAKorey Sewell
Use O3CPU when building instead of AlphaO3CPU. I could use some better python magic in the cpu_models.py file! AUTHORS: add middle initial SConstruct: change from AlphaO3CPU to O3CPU src/cpu/SConscript: edits to build O3CPU instead of AlphaO3CPU src/cpu/cpu_models.py: change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model... Actually, some Python expertise could be used here. The 'env' variable is not passed to this file, so I had to parse through the ARGV to find the ISA... src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use isa_specific.hh src/sim/process.cc: only initi NextNPC if not ALPHA src/cpu/o3/alpha/cpu.cc: alphao3cpu impl src/cpu/o3/alpha/cpu.hh: move AlphaTC to it's own file src/cpu/o3/alpha/cpu_impl.hh: Move AlphaTC to it's own file ... src/cpu/o3/alpha/dyn_inst.cc: src/cpu/o3/alpha/dyn_inst.hh: src/cpu/o3/alpha/dyn_inst_impl.hh: include paths src/cpu/o3/alpha/impl.hh: include paths, set default MaxThreads to 2 instead of 4 src/cpu/o3/alpha/params.hh: set Alpha Specific Params here src/python/m5/objects/O3CPU.py: add O3CPU class src/cpu/o3/SConscript: include isa-specific build files src/cpu/o3/alpha/thread_context.cc: NEW HOME of AlphaTC src/cpu/o3/alpha/thread_context.hh: new home of AlphaTC src/cpu/o3/isa_specific.hh: includes ISA specific files src/cpu/o3/params.hh: base o3 params src/cpu/o3/thread_context.hh: base o3 thread context src/cpu/o3/thread_context_impl.hh: base o3 thead context impl --HG-- rename : src/cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha/cpu.cc rename : src/cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha/cpu.hh rename : src/cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha/cpu_builder.cc rename : src/cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha/cpu_impl.hh rename : src/cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha/dyn_inst.cc rename : src/cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha/dyn_inst.hh rename : src/cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha/dyn_inst_impl.hh rename : src/cpu/o3/alpha_impl.hh => src/cpu/o3/alpha/impl.hh rename : src/cpu/o3/alpha_params.hh => src/cpu/o3/alpha/params.hh rename : src/python/m5/objects/AlphaO3CPU.py => src/python/m5/objects/O3CPU.py extra : convert_revision : d377d6417452ac337bc502f28b2fde907d6b340e
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 15:50:20 +0000