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path: root/src/cpu/o3/cpu.cc
AgeCommit message (Expand)Author
2009-01-24cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.Nathan Binkert
2009-01-21o3cpu: give a name to the activity recorder for better tracingNathan Binkert
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...Gabe Black
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-10-09O3: Generalize the O3 CPU object so it isn't split out by ISA.Gabe Black
2008-09-27gcc: Add extra parens to quell warnings.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-07-01Make the cached virtPort have a thread context so it can do everything that a...Ali Saidi
2008-02-27Add comments in code to describe bug conditions.Korey Sewell
2008-02-27Fix Load/Store Queue squashing after a SMT thread is removed but ensuringKorey Sewell
2008-02-27Fix offset in removeThread() function so that float registers start freeing upKorey Sewell
2008-02-06Make the Event::description() a const functionStephen Hines
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-09-28Update statistics to use cycles properly instead of ticksAli Saidi
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-06-20Don't do checker stuff if the checker is not definedNathan Binkert
2007-04-23Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
2007-04-22Use proper cycles for IPC and CPI equations.Kevin Lim
2007-04-14Add support for microcode and pull out the special branch delay slot handling...Gabe Black
2007-04-13Remove most of the special handling for delay slots since they have to be squ...Gabe Black
2007-04-04Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...Kevin Lim
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23A couple of minor fixes.Kevin Lim
2007-03-09Two fixes:Kevin Lim
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-01-03Merge zizzer:/bk/newmemGabe Black
2006-12-28Implement a stub nnpc for alpha that is read only as npc+4.Gabe Black
2006-12-20<scold> Make sure that variables are always initalized! </scold>Nathan Binkert
2006-12-16Made branch delay slots get squashed, and passed back an NPC and NNPC to star...Gabe Black
2006-12-06Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the a...Gabe Black
2006-11-29Change the connecting of the physPort and virtPort to the memory object below...Kevin Lim
2006-11-19Update Virtual and Physical ports.Kevin Lim
2006-11-09Draining fixes.Kevin Lim
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-18only do this assert after you know you're not switched out or idle.Lisa Hsu
2006-10-09Comment out code that messed up SMT (but will be needed eventually).Kevin Lim
2006-10-09Fix caches plus sampling switch over.Kevin Lim
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