gem5 - gem5

Age	Commit message (Expand)	Author
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu/o3: clean up rename map and free list	Steve Reinhardt
2013-10-15	cpu/o3: clean up scoreboard object	Steve Reinhardt
2013-10-15	cpu/o3: clean up physical register file	Steve Reinhardt
2013-04-22	sim: separate nextCycle() and clockEdge() in clockedObjects	Dam Sunwoo
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-02-15	cpu: Refactor memory system checks	Andreas Sandberg
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
2013-01-07	cpu: Unify the serialization code for all of the CPU models	Andreas Sandberg
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	o3 cpu: Remove unused variables	Andreas Sandberg
2013-01-07	cpu: Rename defer_registration->switched_out	Andreas Sandberg
2013-01-07	cpu: Correctly call parent on switchOut() and takeOverFrom()	Andreas Sandberg
2013-01-07	cpu: Unify SimpleCPU and O3 CPU serialization code	Andreas Sandberg
2013-01-07	cpu: Initialize the O3 pipeline from startup()	Andreas Sandberg
2013-01-07	cpu: Check that the memory system is in the correct mode	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2013-01-07	cpu: rename the misleading inSyscall to noSquashFromTC	Ali Saidi
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-21	Clock: Make Tick unsigned and remove UTick	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	CPU: Unify initMemProxies across CPUs and simulation modes	Andreas Hansson
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-12	cpu: add separate stats for insts/ops both globally and per cpu model	Anthony Gutierrez
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-07	Merge with the main repository again.	Gabe Black
2012-01-07	Merge with main repository.	Gabe Black
2011-12-01	O3: Add stat that counts how many cycles the O3 cpu was quiesced.	Ali Saidi
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-11-01	SE/FS: Expose the same methods on the CPUs in SE and FS modes.	Gabe Black
2011-10-31	SE/FS: Make the functions available from the TC consistent between SE and FS.	Gabe Black
2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
2011-10-30	SE/FS: Build the base process class in FS.	Gabe Black
2011-08-07	O3: Get rid of the unused addToRemoveList function.	Gabe Black
2011-07-10	O3: Make sure fetch doesn't go off into the weeds during speculation.	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-17	O3: Send instruction back to fetch on squash to seed predecoder correctly.	Ali Saidi