Age | Commit message (Expand) | Author |
2015-11-22 | cpu: Fix base FP and CC register index in o3 insertThread() | Nathanael Premillieu |
2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
2015-07-26 | cpu: implements vector registers | Nilay Vaish |
2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
2015-04-03 | cpu: fix system total instructions accounting | Nikos Nikoleris |
2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
2015-02-06 | cpu: Idle CPU status logic revised | Alexandru Dutu |
2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
2014-10-20 | cpu: o3: corrects base FP and CC register index in removeThread() | Nilay Vaish |
2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
2014-09-20 | cpu: Remove unused deallocateContext calls | Mitch Hayenga |
2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
2014-09-03 | cpu: Fix SMT scheduling issue with the O3 cpu | Mitch Hayenga |
2014-06-21 | o3: split load & store queue full cases in rename | Binh Pham |
2014-05-23 | cpu: o3: remove stat totalCommittedInsts | Nilay Vaish |
2014-04-19 | o3: Fix occupancy checks for SMT | Faissal Sleiman |
2014-01-24 | base: add support for probe points and common probes | Matt Horsnell |
2013-12-03 | cpu: call BaseCPU startup() function in o3 cpu | Nilay Vaish |
2013-10-31 | cpu: Construct ROB with cpu params struct instead of each variable | Faissal Sleiman |
2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
2013-10-15 | cpu/o3: clean up rename map and free list | Steve Reinhardt |
2013-10-15 | cpu/o3: clean up scoreboard object | Steve Reinhardt |
2013-10-15 | cpu/o3: clean up physical register file | Steve Reinhardt |
2013-04-22 | sim: separate nextCycle() and clockEdge() in clockedObjects | Dam Sunwoo |
2013-02-15 | sim: Add a system-global option to bypass caches | Andreas Sandberg |
2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
2013-01-12 | x86: Changes to decoder, corrects 9376 | Nilay Vaish |
2013-01-07 | cpu: Unify the serialization code for all of the CPU models | Andreas Sandberg |
2013-01-07 | cpu: Rewrite O3 draining to avoid stopping in microcode | Andreas Sandberg |
2013-01-07 | o3 cpu: Remove unused variables | Andreas Sandberg |
2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
2013-01-07 | cpu: Correctly call parent on switchOut() and takeOverFrom() | Andreas Sandberg |
2013-01-07 | cpu: Unify SimpleCPU and O3 CPU serialization code | Andreas Sandberg |
2013-01-07 | cpu: Initialize the O3 pipeline from startup() | Andreas Sandberg |
2013-01-07 | cpu: Check that the memory system is in the correct mode | Andreas Sandberg |
2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
2013-01-07 | cpu: rename the misleading inSyscall to noSquashFromTC | Ali Saidi |
2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
2012-08-28 | Clock: Rework clocks to avoid tick-to-cycle transformations | Andreas Hansson |
2012-08-21 | Clock: Make Tick unsigned and remove UTick | Andreas Hansson |