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path: root/src/cpu/o3/cpu.hh
AgeCommit message (Expand)Author
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-20cpu: Remove unused deallocateContext callsMitch Hayenga
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-01-24base: add support for probe points and common probesMatt Horsnell
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu/o3: clean up rename map and free listSteve Reinhardt
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2013-01-07o3 cpu: Remove unused variablesAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Initialize the O3 pipeline from startup()Andreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-17MEM: Add port proxies instead of non-structural portsAndreas Hansson
2012-01-07Merge with the main repository again.Gabe Black
2011-12-01O3: Add stat that counts how many cycles the O3 cpu was quiesced.Ali Saidi
2011-11-18SE/FS: Get rid of includes of config/full_system.hh.Gabe Black
2011-11-01SE/FS: Expose the same methods on the CPUs in SE and FS modes.Gabe Black
2011-10-31SE/FS: Make the functions available from the TC consistent between SE and FS.Gabe Black
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-08-07O3: Get rid of the unused addToRemoveList function.Gabe Black
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-04-15includes: sort all includesNathan Binkert
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