gem5 - gem5

Age	Commit message (Expand)	Author
2016-02-10	mem: Deduce if cache should forward snoops	Andreas Hansson
2016-01-17	cpu: remove unnecessary data ptr from O3 internal read() funcs	Steve Reinhardt
2015-10-12	misc: Add explicit overrides and fix other clang >= 3.5 issues	Andreas Hansson
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-09-30	cpu,isa,mem: Add per-thread wakeup logic	Mitch Hayenga
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-07-07	sim: Refactor and simplify the drain API	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-07-07	sim: Refactor the serialization base class	Andreas Sandberg
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2014-11-06	x86 isa: This patch attempts an implementation at mwait.	Marc Orr
2014-09-27	arch: Use const StaticInstPtr references where possible	Andreas Hansson
2014-09-20	cpu: Remove unused deallocateContext calls	Mitch Hayenga
2014-09-20	alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate	Mitch Hayenga
2014-09-19	arch: Pass faults by const reference where possible	Andreas Hansson
2014-05-23	cpu: o3: remove stat totalCommittedInsts	Nilay Vaish
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu/o3: clean up rename map and free list	Steve Reinhardt
2013-03-26	cpu: Remove CpuPort and use MasterPort in the CPU classes	Andreas Hansson
2013-02-15	cpu: Refactor memory system checks	Andreas Sandberg
2013-01-07	cpu: Unify the serialization code for all of the CPU models	Andreas Sandberg
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	o3 cpu: Remove unused variables	Andreas Sandberg
2013-01-07	cpu: Rename defer_registration->switched_out	Andreas Sandberg
2013-01-07	cpu: Initialize the O3 pipeline from startup()	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-12	cpu: add separate stats for insts/ops both globally and per cpu model	Anthony Gutierrez
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2012-01-07	Merge with the main repository again.	Gabe Black
2011-12-01	O3: Add stat that counts how many cycles the O3 cpu was quiesced.	Ali Saidi
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-11-01	SE/FS: Expose the same methods on the CPUs in SE and FS modes.	Gabe Black