| Age | Commit message (Expand) | Author |
|---|
| 2019-05-11 | cpu,mem: Add support for partial loads/stores and wide mem. accesses | Giacomo Gabrielli |
| 2019-04-30 | cpu: alpha: Delete all occurrances of the simPalCheck function. | Gabe Black |
| 2019-04-30 | cpu: Remove hwrei from the generic interfaces. | Gabe Black |
| 2019-04-28 | mem: Minimize the use of MemObject. | Gabe Black |
| 2019-02-08 | cpu: support atomic memory request type with AtomicOpFunctor | Tuan Ta |
| 2019-02-08 | cpu: fixed how O3 CPU executes an exit system call | Tuan Ta |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-24 | cpu-o3: O3 LSQ Generalisation | Rekai Gonzalez-Alberquilla |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
| 2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
| 2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-07-12 | cpu: Refactor some Event subclasses to lambdas | Sean Wilson |
| 2017-07-05 | cpu: Added interface for vector reg file | Rekai Gonzalez-Alberquilla |
| 2017-07-05 | cpu: Physical register structural + flat indexing | Nathanael Premillieu |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2016-02-10 | mem: Deduce if cache should forward snoops | Andreas Hansson |
| 2016-01-17 | cpu: remove unnecessary data ptr from O3 internal read() funcs | Steve Reinhardt |
| 2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-09-20 | cpu: Remove unused deallocateContext calls | Mitch Hayenga |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-05-23 | cpu: o3: remove stat totalCommittedInsts | Nilay Vaish |
| 2014-01-24 | base: add support for probe points and common probes | Matt Horsnell |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-10-15 | cpu/o3: clean up rename map and free list | Steve Reinhardt |
| 2013-03-26 | cpu: Remove CpuPort and use MasterPort in the CPU classes | Andreas Hansson |
| 2013-02-15 | cpu: Refactor memory system checks | Andreas Sandberg |
| 2013-01-07 | cpu: Unify the serialization code for all of the CPU models | Andreas Sandberg |
| 2013-01-07 | cpu: Rewrite O3 draining to avoid stopping in microcode | Andreas Sandberg |
| 2013-01-07 | o3 cpu: Remove unused variables | Andreas Sandberg |
| 2013-01-07 | cpu: Rename defer_registration->switched_out | Andreas Sandberg |
| 2013-01-07 | cpu: Initialize the O3 pipeline from startup() | Andreas Sandberg |
| 2013-01-07 | arch: Make the ISA class inherit from SimObject | Andreas Sandberg |
