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path: root/src/cpu/o3/cpu.hh
AgeCommit message (Expand)Author
2019-09-23cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>Jordi Vaquero
2019-08-28cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.Gabe Black
2019-08-28cpu: Move the instruction port into o3's fetch stage.Gabe Black
2019-08-28cpu: Move O3's data port into the LSQ.Gabe Black
2019-07-16cpu: isDrained renamed to isCpuDrainedGiacomo Travaglini
2019-05-11cpu,mem: Add support for partial loads/stores and wide mem. accessesGiacomo Gabrielli
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-02-08cpu: support atomic memory request type with AtomicOpFunctorTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2019-01-24cpu-o3: O3 LSQ GeneralisationRekai Gonzalez-Alberquilla
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-07-12cpu: Refactor some Event subclasses to lambdasSean Wilson
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-09-30cpu,isa,mem: Add per-thread wakeup logicMitch Hayenga
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-20cpu: Remove unused deallocateContext callsMitch Hayenga
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-01-24base: add support for probe points and common probesMatt Horsnell
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu/o3: clean up rename map and free listSteve Reinhardt
2013-03-26cpu: Remove CpuPort and use MasterPort in the CPU classesAndreas Hansson
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg