gem5 - gem5

Age	Commit message (Expand)	Author
2013-02-15	o3: fix tick used for renaming and issue with range selection	Matt Horsnell
2013-02-15	cpu: fix case with o3 cpu blocking and unblocking decode in cycle	Ali Saidi
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-03-21	O3: Fix size of skid buffer between fetch and decode when widths are different	Brian Grayson
2012-02-13	BP: Fix several Branch Predictor issues.	Mrinmoy Ghosh
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-09	O3: Remove some asserts that no longer seem to be valid.	Ali Saidi
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-08-14	O3: When squashing, restore the macroop that should be used for fetching.	Gabe Black
2011-07-15	O3: Create a pipeline activity viewer for the O3 CPU model.	Giacomo Gabrielli
2011-04-19	stats: rename stats so they can be used as python expressions	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: fix up code after sorting	Nathan Binkert
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-04-18	o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...	Korey Sewell
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2007-04-14	Add support for microcode and pull out the special branch delay slot handling...	Gabe Black
2007-04-13	Remove most of the special handling for delay slots since they have to be squ...	Gabe Black
2007-04-04	Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...	Kevin Lim
2007-04-02	Remove/comment out DPRINTFs that were causing a segfault.	Kevin Lim
2007-01-03	Merge zizzer:/bk/newmem	Gabe Black
2006-12-28	Some fixes for decode stage branches without delay slots. This will need some...	Gabe Black
2006-12-20	don't use (*activeThreads).begin(), use activeThreads->blah().	Nathan Binkert
2006-12-16	Make the decoder use the new setup in the dyninsts for branch prediction.	Gabe Black
2006-08-31	add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throug...	Korey Sewell
2006-08-15	Cleaned up include files and got rid of many using directives in header files.	Gabe Black
2006-07-23	This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...	Korey Sewell
2006-07-06	Fix the O3CPU to support the multi-pass method for checking if the system has...	Kevin Lim
2006-07-06	Support for draining, and the new method of switching out. Now switching out...	Kevin Lim
2006-06-16	Two updates that got combined into one ChangeSet accidentally. They're both ...	Kevin Lim
2006-06-14	Minor code cleanup of BaseDynInst.	Kevin Lim
2006-06-12	Fix output messages.	Kevin Lim
2006-06-05	Fixes to get new CPU model working for simple test case. The CPU does not ye...	Kevin Lim
2006-06-04	Merge ktlim@zamp:/z/ktlim2/clean/m5-o3	Kevin Lim
2006-06-02	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-30	Merge ktlim@zizzer:/bk/m5	Kevin Lim
2006-05-22	New directory structure:	Steve Reinhardt