| Age | Commit message (Expand) | Author |
|---|---|---|
| 2009-07-08 | Registers: Get rid of the float register width parameter. | Gabe Black |
| 2008-10-20 | O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo... | Ali Saidi |
| 2008-10-11 | CPU: Eliminate the simPalCheck funciton. | Gabe Black |
| 2008-10-11 | CPU: Eliminate the hwrei function. | Gabe Black |
| 2008-10-09 | O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA. | Gabe Black |
| 2008-02-05 | Add base ARM code to M5 | Stephen Hines |
| 2007-03-05 | Added an x86 dyninst | Gabe Black |
| 2006-08-11 | Started to add support for O3 for sparc. | Gabe Black |
| 2006-07-23 | This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,... | Korey Sewell |
| 2006-07-06 | Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALP... | Korey Sewell |
| 2006-07-06 | Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s... | Korey Sewell |
| 2006-07-06 | more steps toward O3 SMT | Korey Sewell |
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