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path: root/src/cpu/o3/dyn_inst.hh
AgeCommit message (Expand)Author
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-05-15misc: Appease gcc 5.1Andreas Hansson
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-03-12alpha: Small removal of dead comments/code from alpha ISAPaul Rosenfeld
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
2013-02-15cpu: Avoid duplicate entries in tracking structures for writes to misc regsGeoffrey Blake
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
2013-01-07cpu: rename the misleading inSyscall to noSquashFromTCAli Saidi
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2011-11-01SE/FS: Expose the same methods on the CPUs in SE and FS modes.Gabe Black
2011-09-19Syscall: Make the syscall function available in both SE and FS modes.Gabe Black
2011-08-14O3: Add a pointer to the macroop for a microop in the dyninst.Gabe Black
2011-08-02O3: Get rid of the raw ExtMachInst constructor on DynInsts.Gabe Black
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
2011-04-15includes: sort all includesNathan Binkert
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black
2008-10-09O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.Gabe Black
2008-02-05Add base ARM code to M5Stephen Hines
2007-03-05Added an x86 dyninstGabe Black
2006-08-11Started to add support for O3 for sparc.Gabe Black
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-07-06Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALP...Korey Sewell
2006-07-06Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s...Korey Sewell
2006-07-06more steps toward O3 SMTKorey Sewell