gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-05-15	misc: Appease gcc 5.1	Andreas Hansson
2014-09-27	arch: Use const StaticInstPtr references where possible	Andreas Hansson
2014-09-19	arch: Pass faults by const reference where possible	Andreas Hansson
2014-09-03	arch, cpu: Factor out the ExecContext into a proper base class	Andreas Sandberg
2014-03-12	alpha: Small removal of dead comments/code from alpha ISA	Paul Rosenfeld
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-10-15	cpu: clean up architectural register classification	Steve Reinhardt
2013-02-15	cpu: Avoid duplicate entries in tracking structures for writes to misc regs	Geoffrey Blake
2013-02-15	o3: fix tick used for renaming and issue with range selection	Matt Horsnell
2013-01-07	cpu: rename the misleading inSyscall to noSquashFromTC	Ali Saidi
2012-09-25	CPU: Add abandoned instructions to O3 Pipe Viewer	Djordje Kovacevic
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2011-11-01	SE/FS: Expose the same methods on the CPUs in SE and FS modes.	Gabe Black
2011-09-19	Syscall: Make the syscall function available in both SE and FS modes.	Gabe Black
2011-08-14	O3: Add a pointer to the macroop for a microop in the dyninst.	Gabe Black
2011-08-02	O3: Get rid of the raw ExtMachInst constructor on DynInsts.	Gabe Black
2011-07-15	O3: Create a pipeline activity viewer for the O3 CPU model.	Giacomo Gabrielli
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black
2008-10-20	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...	Ali Saidi
2008-10-11	CPU: Eliminate the simPalCheck funciton.	Gabe Black
2008-10-11	CPU: Eliminate the hwrei function.	Gabe Black
2008-10-09	O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.	Gabe Black
2008-02-05	Add base ARM code to M5	Stephen Hines
2007-03-05	Added an x86 dyninst	Gabe Black
2006-08-11	Started to add support for O3 for sparc.	Gabe Black
2006-07-23	This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...	Korey Sewell
2006-07-06	Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALP...	Korey Sewell
2006-07-06	Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s...	Korey Sewell
2006-07-06	more steps toward O3 SMT	Korey Sewell