gem5 - gem5

Age	Commit message (Expand)	Author
2011-04-15	includes: sort all includes	Nathan Binkert
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black
2008-10-20	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...	Ali Saidi
2008-10-11	CPU: Eliminate the simPalCheck funciton.	Gabe Black
2008-10-11	CPU: Eliminate the hwrei function.	Gabe Black
2008-10-09	O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.	Gabe Black
2008-02-05	Add base ARM code to M5	Stephen Hines
2007-03-05	Added an x86 dyninst	Gabe Black
2006-08-11	Started to add support for O3 for sparc.	Gabe Black
2006-07-23	This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...	Korey Sewell
2006-07-06	Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALP...	Korey Sewell
2006-07-06	Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s...	Korey Sewell
2006-07-06	more steps toward O3 SMT	Korey Sewell