gem5 - gem5

Age	Commit message (Expand)	Author
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-29	Implement Ali's review feedback.	Gabe Black
2011-11-01	SE/FS: Expose the same methods on the CPUs in SE and FS modes.	Gabe Black
2011-09-19	Syscall: Make the syscall function available in both SE and FS modes.	Gabe Black
2011-08-14	O3: Add a pointer to the macroop for a microop in the dyninst.	Gabe Black
2011-08-02	O3: Get rid of the raw ExtMachInst constructor on DynInsts.	Gabe Black
2011-07-15	O3: Create a pipeline activity viewer for the O3 CPU model.	Giacomo Gabrielli
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-11-15	O3: prevent a squash when completeAcc() modifies misc reg through TC.	Min Kyu Jeong
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-09-20	CPU: Fix O3 and possible InOrder segfaults in FS.	Gabe Black
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2009-02-26	CPA: Add code to automatically record function symbols as CPU executes.	Ali Saidi
2008-10-20	O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...	Ali Saidi
2008-10-11	CPU: Eliminate the simPalCheck funciton.	Gabe Black
2008-10-11	CPU: Eliminate the hwrei function.	Gabe Black
2008-10-09	O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.	Gabe Black