gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-03	cpu: Fix o3 front-end pipeline interlock behavior	Mitch Hayenga
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2013-11-15	cpu: allow the fetch buffer to be smaller than a cache line	Anthony Gutierrez
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	cpu: Initialize the O3 pipeline from startup()	Andreas Sandberg
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2011-09-09	Decode: Pull instruction decoding out of the StaticInst class into its own.	Gabe Black
2011-08-14	O3: When squashing, restore the macroop that should be used for fetching.	Gabe Black
2011-07-10	O3: Fix up pipelining icache accesses in fetch stage to function properly	Geoffrey Blake
2011-07-10	O3: Make sure fetch doesn't go off into the weeds during speculation.	Ali Saidi
2011-05-23	O3: Fix issue with interrupts/faults occuring in the middle of a macro-op	Geoffrey Blake
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-17	O3: Send instruction back to fetch on squash to seed predecoder correctly.	Ali Saidi
2011-02-23	O3: Fix bug when a squash occurs right before TLB miss returns.	Ali Saidi
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2011-01-18	O3: Support timing translations for O3 CPU fetch.	Ali Saidi
2011-01-18	O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.	Min Kyu Jeong
2011-01-03	Move sched_list.hh and timebuf.hh from src/base to src/cpu.	Steve Reinhardt
2010-11-15	O3: Make O3 support variably lengthed instructions.	Gabe Black
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-23	ISA: Get rid of old, unused utility functions cluttering up the ISAs.	Gabe Black
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-03-05	stats: Fix all stats usages to deal with template fixes	Nathan Binkert
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2007-06-19	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
2007-05-21	Change getDeviceAddressRanges to use bool for snoop arg.	Steve Reinhardt
2007-04-14	Add support for microcode and pull out the special branch delay slot handling...	Gabe Black
2007-04-13	Remove most of the special handling for delay slots since they have to be squ...	Gabe Black
2007-04-04	Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...	Kevin Lim
2007-03-29	Update code so that the O3 CPU can handle not initially having anything hooke...	Kevin Lim
2007-03-15	Make the predecoder an object with it's own switched header file. Start addin...	Gabe Black
2006-12-28	Phased out DelaySlotInfo.	Gabe Black
2006-12-16	Merge zizzer:/bk/newmem	Gabe Black
2006-12-16	Made branch delay slots get squashed, and passed back an NPC and NNPC to star...	Gabe Black
2006-12-15	little fixes i noticed while searching for reason for address range issues (b...	Lisa Hsu
2006-11-13	Make CPU models signal to update the snoop ranges	Ron Dreslinski
2006-10-31	Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...	Kevin Lim
2006-10-19	refactor code for the packet, get rid of packet_impl.hh	Nathan Binkert
2006-10-09	Have cpus send snoop ranges	Ron Dreslinski
2006-07-23	This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...	Korey Sewell