gem5 - gem5

Age	Commit message (Expand)	Author
2009-09-26	O3: Mark fetch stage as active if it faults.	Steve Reinhardt
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-08-01	Fix setting of INST_FETCH flag for O3 CPU.	Steve Reinhardt
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-04-18	o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...	Korey Sewell
2009-04-15	o3: handle fetch with no active threads correctly.	Steve Reinhardt
2009-04-08	tlb: More fixing of unified TLB	Nathan Binkert
2009-04-08	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	Gabe Black
2009-03-04	O3: Make numThreads error message more helpful.	Steve Reinhardt
2009-02-25	ISA: Replace the translate functions in the TLBs with translateAtomic.	Gabe Black
2009-02-25	CPU: Get rid of translate... functions from various interface classes.	Gabe Black
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2007-08-26	Merge with head	Gabe Black
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-08-13	O3: Set up the predicted npc and nnpc for a fault carrying noop so that it do...	Gabe Black
2007-07-29	Merge Gabe's changes from head.	Steve Reinhardt
2007-07-28	Turn the instruction tracing code into pluggable sim objects.	Gabe Black
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-06-21	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
2007-06-20	Fix compiler errors.	Gabe Black
2007-06-19	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
2007-06-19	Make branches work by repopulating the predecoder every time through. This is...	Gabe Black
2007-06-13	Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "more...	Gabe Black
2007-06-09	Use the right type	Nathan Binkert
2007-06-01	Fix typo so m5.fast will compile	Nathan Binkert
2007-06-01	don't generate trace data unless tracing is on	Ali Saidi
2007-04-15	Make an inner loop which pulls microops out of macroops. These aren't checked...	Gabe Black
2007-04-14	Add support for microcode and pull out the special branch delay slot handling...	Gabe Black
2007-04-13	Remove most of the special handling for delay slots since they have to be squ...	Gabe Black
2007-04-04	Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...	Kevin Lim
2007-04-02	Remove/comment out DPRINTFs that were causing a segfault.	Kevin Lim
2007-03-29	Update code so that the O3 CPU can handle not initially having anything hooke...	Kevin Lim
2007-03-23	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2007-03-23	Two fixes:	Kevin Lim
2007-03-15	Make the predecoder an object with it's own switched header file. Start addin...	Gabe Black
2007-03-13	Replaced makeExtMI with predecode.	Gabe Black
2007-03-06	Move all of the parameters of the Root SimObject so they are	Nathan Binkert
2007-02-07	Make memory commands dense again to avoid cache stat table explosion.	Steve Reinhardt
2007-01-29	A minor hack to get branch prediction to behave like before on Alpha.	Gabe Black
2007-01-03	Merge zizzer:/bk/newmem	Gabe Black
2006-12-28	Phased out DelaySlotInfo.	Gabe Black
2006-12-20	don't use (*activeThreads).begin(), use activeThreads->blah().	Nathan Binkert
2006-12-20	Fixes to get ALPHA_FS and ALPHA_SE to compile again.	Gabe Black
2006-12-16	Make fetch detect when a branch is happening, rather than trying to compute w...	Gabe Black