summaryrefslogtreecommitdiff
path: root/src/cpu/o3/fetch_impl.hh
AgeCommit message (Expand)Author
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2014-12-02mem: Assume all dynamic packet data is array allocatedAndreas Hansson
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-10-11cpu: Fix o3 SMT IQCount bugAndrew Lukefahr
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-09cpu: Only iterate over possible threads on the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 quiesce fetch bugMitch Hayenga
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 front-end pipeline interlock behaviorMitch Hayenga
2014-06-30cpu: implement a bi-mode branch predictorAnthony Gutierrez
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-08-19cpu: Fix a bug in the O3 CPU introduced by the cache line patchAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-04-22cpu: fix a switching issue with the o3 cpu.Ali Saidi
2013-03-04cpu: fix a switching issue with the o3 cpu.Ali Saidi
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2013-01-07cpu: Initialize the O3 pipeline from startup()Andreas Sandberg
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-11O3: Add fatal when fetchWidth > Impl::MaxWidth.Brian Grayson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
2012-02-10O3 Fetch: Check if PC is pointing to Microcode ROMNilay Vaish
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake