summaryrefslogtreecommitdiff
path: root/src/cpu/o3/fetch_impl.hh
AgeCommit message (Collapse)Author
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end.
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
Force all non-default ports to provide a name and an owner in the constructor.
2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-08-13O3: Set up the predicted npc and nnpc for a fault carrying noop so that it ↵Gabe Black
doesn't cause a false branch mispredict. --HG-- extra : convert_revision : 2820597cc966cd7b128cef0dab48fe05089533d7
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
--HG-- extra : convert_revision : d00b7b09c7f19bc0e37b385ef7c124f69c0e917f
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro src/cpu/o3/fetch_impl.hh: hand merge --HG-- extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
2007-06-20Fix compiler errors.Gabe Black
--HG-- extra : convert_revision : 2b10076a24cb36cb748e299011ae691f09c158cd
2007-06-19Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro src/cpu/base_dyn_inst_impl.hh: src/cpu/o3/fetch_impl.hh: Hand merge --HG-- extra : convert_revision : 0c0692033ac30133672d8dfe1f1a27e9d9e95a3d
2007-06-19Make branches work by repopulating the predecoder every time through. This ↵Gabe Black
is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. --HG-- extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
2007-06-13Seperate the pc-pc and the pc of the incoming bytes, and get rid of the ↵Gabe Black
"moreBytes" which just takes a MachInst. src/arch/x86/predecoder.cc: Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes. --HG-- extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
2007-06-09Use the right typeNathan Binkert
--HG-- extra : convert_revision : b5ca3153ca786ea4e86bfe83f7760ba9ee41a882
2007-06-01Fix typo so m5.fast will compileNathan Binkert
--HG-- extra : convert_revision : 8ceb816c17108d7cb65cb46d8dc2bd2753b0e0f0
2007-06-01don't generate trace data unless tracing is onAli Saidi
--HG-- extra : convert_revision : 3953ace8d481d758d6e0d89183c0a7e7bebcf681
2007-04-15Make an inner loop which pulls microops out of macroops. These aren't ↵Gabe Black
checked for control flow because we can pull out microops until we run out of buffer. This prevents microops from being interpretted as branches because the pc doesn't become npc. --HG-- extra : convert_revision : 9fff7c6c32900692bbc567ecb75701c9c73da259
2007-04-14Add support for microcode and pull out the special branch delay slot ↵Gabe Black
handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. --HG-- extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
2007-04-13Remove most of the special handling for delay slots since they have to be ↵Gabe Black
squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect. --HG-- extra : convert_revision : b42c4eb28b4fbba66c65cbd0a5033bf886c1532d
2007-04-04Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU ↵Kevin Lim
functions. src/cpu/o3/alpha/cpu_impl.hh: Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions. --HG-- extra : convert_revision : 74f4b1f5fb6f95a56081f367cce7ff44acb5688a
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243. src/cpu/o3/commit_impl.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob_impl.hh: Remove/comment out DPRINTFs that were causing a segfault. --HG-- extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
2007-03-29Update code so that the O3 CPU can handle not initially having anything ↵Kevin Lim
hooked up to its ports. This fixes the segfault Ali recently found when using sampling. src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: Update code so that the O3 CPU can handle not initially having anything hooked up to its ports. --HG-- extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2 src/cpu/base_dyn_inst.hh: Hand merge. Line is no longer needed because it's handled in the ISA. --HG-- extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
2007-03-23Two fixes:Kevin Lim
1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access. 2. load-load ordering is maintained. src/cpu/base_dyn_inst.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. Also include some functions to allow certain status bits to be cleared. src/cpu/base_dyn_inst_impl.hh: Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out. src/cpu/o3/fetch_impl.hh: General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called. src/cpu/o3/lsq_unit.hh: Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system. Also be sure to not store-load forward from an uncacheable store. src/cpu/o3/lsq_unit_impl.hh: Check to make sure load-load ordering was maintained. Also handle requests a little more correctly. --HG-- extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f
2007-03-15Make the predecoder an object with it's own switched header file. Start ↵Gabe Black
adding predecoding functionality to x86. src/arch/SConscript: src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/cpu/base.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/static_inst.hh: src/arch/alpha/predecoder.hh: src/arch/mips/predecoder.hh: src/arch/sparc/predecoder.hh: Make the predecoder an object with it's own switched header file. --HG-- extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
2007-03-13Replaced makeExtMI with predecode.Gabe Black
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. --HG-- extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-01-29A minor hack to get branch prediction to behave like before on Alpha.Gabe Black
--HG-- extra : convert_revision : 1eaabd13c72aa42c512a04d162a87491818bc621
2007-01-03Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : f4a05accb8fa24d425dd818b1b7f268378180e99
2006-12-28Phased out DelaySlotInfo.Gabe Black
--HG-- extra : convert_revision : ab48db10caf38137300da63078aa9360f46b9631
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
Also don't call (*activeThreads).end() over and over. Just call activeThreads->end() once and save the result. Make sure we always check that there are elements in the list before we grab the first one. --HG-- extra : convert_revision : d769d8ed52da99532d57a9bbc93e92ddf22b7e58
2006-12-20Fixes to get ALPHA_FS and ALPHA_SE to compile again.Gabe Black
--HG-- extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-16Make fetch detect when a branch is happening, rather than trying to compute ↵Gabe Black
when. --HG-- extra : convert_revision : 1a8edc004570abb48e6c4cdf1b43c5699866838e
2006-12-16Made branch delay slots get squashed, and passed back an NPC and NNPC to ↵Gabe Black
start fetching from. --HG-- extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
2006-12-11Fix for fetch to use the icache's block size to generate proper access size.Kevin Lim
--HG-- extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
2006-12-06Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/cpu/o3/commit_impl.hh: Hand Merge --HG-- extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
2006-12-06Added a DPRINTF to print out the actual value pulled from memory.Gabe Black
--HG-- extra : convert_revision : 18780f753a7e98f8de3047dd6781b944b0826b4e
2006-12-02Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should ↵Kevin Lim
make sure these changes (commit especially) work okay. src/cpu/o3/commit_impl.hh: src/cpu/o3/fetch_impl.hh: Fixes for MIPS_SE compile. --HG-- extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
2006-11-13Make CPU models signal to update the snoop rangesRon Dreslinski
--HG-- extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
2006-11-12Fix for regression failure.Kevin Lim
src/cpu/o3/fetch_impl.hh: Fetch needs to make sure it isn't waiting on an Icache access. --HG-- extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
2006-11-12Merge ktlim@zamp:./local/clean/tmp/test-regressKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix --HG-- extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
2006-11-12Updates to support new interrupt processing and removal of PcPAL.Kevin Lim
src/arch/alpha/interrupts.hh: No need for this now that the ThreadContext is being used to set these IPRs in interrupts. Also split up the interrupt checking from the updating of the IPL and interrupt summary. src/arch/alpha/tlb.cc: Check the PC for whether or not it's in PAL mode, not the addr. src/cpu/o3/alpha/cpu.hh: Split up getting the interrupt from actually processing the interrupt. src/cpu/o3/alpha/cpu_impl.hh: Splut up the processing of interrupts. src/cpu/o3/commit_impl.hh: Update for ISA-oriented interrupt changes. src/cpu/o3/fetch_impl.hh: Fix broken if statement from PcPAL updates, and properly populate the request fields. Also more debugging output. src/cpu/ozone/cpu_impl.hh: Updates for ISA-oriented interrupt stuff. src/cpu/ozone/front_end_impl.hh: Populate request fields properly. src/cpu/simple/base.cc: Update for interrupt stuff. --HG-- extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
2006-11-10Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 16:03:18 +0000