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path: root/src/cpu/o3/fetch_impl.hh
AgeCommit message (Expand)Author
2009-04-15o3: handle fetch with no active threads correctly.Steve Reinhardt
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-04O3: Make numThreads error message more helpful.Steve Reinhardt
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2007-08-26Merge with headGabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-13O3: Set up the predicted npc and nnpc for a fault carrying noop so that it do...Gabe Black
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-06-20Fix compiler errors.Gabe Black
2007-06-19Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-06-19Make branches work by repopulating the predecoder every time through. This is...Gabe Black
2007-06-13Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "more...Gabe Black
2007-06-09Use the right typeNathan Binkert
2007-06-01Fix typo so m5.fast will compileNathan Binkert
2007-06-01don't generate trace data unless tracing is onAli Saidi
2007-04-15Make an inner loop which pulls microops out of macroops. These aren't checked...Gabe Black
2007-04-14Add support for microcode and pull out the special branch delay slot handling...Gabe Black
2007-04-13Remove most of the special handling for delay slots since they have to be squ...Gabe Black
2007-04-04Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...Kevin Lim
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
2007-03-29Update code so that the O3 CPU can handle not initially having anything hooke...Kevin Lim
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Two fixes:Kevin Lim
2007-03-15Make the predecoder an object with it's own switched header file. Start addin...Gabe Black
2007-03-13Replaced makeExtMI with predecode.Gabe Black
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2007-01-29A minor hack to get branch prediction to behave like before on Alpha.Gabe Black
2007-01-03Merge zizzer:/bk/newmemGabe Black
2006-12-28Phased out DelaySlotInfo.Gabe Black
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
2006-12-20Fixes to get ALPHA_FS and ALPHA_SE to compile again.Gabe Black
2006-12-16Make fetch detect when a branch is happening, rather than trying to compute w...Gabe Black
2006-12-16Made branch delay slots get squashed, and passed back an NPC and NNPC to star...Gabe Black
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
2006-12-11Fix for fetch to use the icache's block size to generate proper access size.Kevin Lim
2006-12-06Merge zizzer:/bk/newmemGabe Black
2006-12-06Added a DPRINTF to print out the actual value pulled from memory.Gabe Black
2006-12-02Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make...Kevin Lim
2006-11-13Make CPU models signal to update the snoop rangesRon Dreslinski
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