Age | Commit message (Collapse) | Author |
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doesn't cause a false branch mispredict.
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These need to be refined a little still and given parameters.
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now encoded in cmd field.
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into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro
src/cpu/o3/fetch_impl.hh:
hand merge
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into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro
src/cpu/base_dyn_inst_impl.hh:
src/cpu/o3/fetch_impl.hh:
Hand merge
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extra : convert_revision : 0c0692033ac30133672d8dfe1f1a27e9d9e95a3d
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is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though.
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extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
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"moreBytes" which just takes a MachInst.
src/arch/x86/predecoder.cc:
Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes.
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checked for control flow because we can pull out microops until we run out of buffer. This prevents microops from being interpretted as branches because the pc doesn't become npc.
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extra : convert_revision : 9fff7c6c32900692bbc567ecb75701c9c73da259
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handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect.
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squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect.
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extra : convert_revision : b42c4eb28b4fbba66c65cbd0a5033bf886c1532d
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functions.
src/cpu/o3/alpha/cpu_impl.hh:
Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.
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The removed ones were unnecessary. The commented out ones could be useful in the future, should this problem get fixed. See flyspray task #243.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/o3/rob_impl.hh:
Remove/comment out DPRINTFs that were causing a segfault.
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extra : convert_revision : b5aeda1c6300dfde5e0a3e9b8c4c5f6fa00b9862
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hooked up to its ports. This fixes the segfault Ali recently found when using sampling.
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
Update code so that the O3 CPU can handle not initially having anything hooked up to its ports.
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extra : convert_revision : 04bcef44e754735d821509ebd69b0ef9c8ef8e2c
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into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2
src/cpu/base_dyn_inst.hh:
Hand merge. Line is no longer needed because it's handled in the ISA.
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extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680
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1. Requests are handled more properly now. They assume the memory system takes control of the request upon sending out an access.
2. load-load ordering is maintained.
src/cpu/base_dyn_inst.hh:
Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.
Also include some functions to allow certain status bits to be cleared.
src/cpu/base_dyn_inst_impl.hh:
Update how requests are handled. The BaseDynInst should not be able to hold a pointer to the request because the request becomes owned by the memory system once it is sent out.
src/cpu/o3/fetch_impl.hh:
General correctness fixes. retryPkt is not necessarily always set, so handle it properly. Also consider the cache unblocked only when recvRetry is called.
src/cpu/o3/lsq_unit.hh:
Handle requests a little more correctly. Now that the requests aren't pointed to by the DynInst, be sure to delete the request if it's not being used by the memory system.
Also be sure to not store-load forward from an uncacheable store.
src/cpu/o3/lsq_unit_impl.hh:
Check to make sure load-load ordering was maintained.
Also handle requests a little more correctly.
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extra : convert_revision : e86bead2886d02443cf77bf7a7a1492845e1690f
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adding predecoding functionality to x86.
src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
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extra : convert_revision : 77206e29089130e86b97164c30022a062699ba86
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Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
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extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
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directly configured by python. Move stuff from root.(cc|hh) to
core.(cc|hh) since it really belogs there now.
In the process, simplify how ticks are used in the python code.
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extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
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Created MemCmd class to wrap enum and provide handy methods to
check attributes, convert to string/int, etc.
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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Also don't call (*activeThreads).end() over and over. Just
call activeThreads->end() once and save the result.
Make sure we always check that there are elements in the list
before we grab the first one.
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when.
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start fetching from.
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extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
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into zower.eecs.umich.edu:/eecshome/m5/newmem
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into zower.eecs.umich.edu:/eecshome/m5/newmem
src/cpu/o3/commit_impl.hh:
Hand Merge
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extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
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extra : convert_revision : 18780f753a7e98f8de3047dd6781b944b0826b4e
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make sure these changes (commit especially) work okay.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch_impl.hh:
Fixes for MIPS_SE compile.
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src/cpu/o3/fetch_impl.hh:
Fetch needs to make sure it isn't waiting on an Icache access.
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extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
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src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
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extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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but isn't tested. Other architectures will not.
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are in PAL mode, however.
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src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
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extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
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for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
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extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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change warning to a DPRINTF.
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extra : convert_revision : 819bade049d7ffd97d316051c99146ece5e3a651
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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