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path: root/src/cpu/o3/fetch_impl.hh
AgeCommit message (Expand)Author
2011-07-10O3: Fix up pipelining icache accesses in fetch stage to function properlyGeoffrey Blake
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-06-10o3: missing newlines on some dprintfsKorey Sewell
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-25O3CPU: Fix iqCount and lsqCount SMT fetch policies.Timothy M. Jones
2011-02-23O3: Fix bug when a squash occurs right before TLB miss returns.Ali Saidi
2011-02-13O3: Fetch from the microcode ROM when needed.Gabe Black
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
2011-02-02O3: Fix a style bug in O3.Gabe Black
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18O3: Fix mispredicts from non control instructions.Matt Horsnell
2011-01-18O3: Support timing translations for O3 CPU fetch.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2009-09-26O3: Mark fetch stage as active if it faults.Steve Reinhardt
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-04-18o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...Korey Sewell
2009-04-15o3: handle fetch with no active threads correctly.Steve Reinhardt
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-04O3: Make numThreads error message more helpful.Steve Reinhardt
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2007-08-26Merge with headGabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-13O3: Set up the predicted npc and nnpc for a fault carrying noop so that it do...Gabe Black
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-06-20Fix compiler errors.Gabe Black