summaryrefslogtreecommitdiff
path: root/src/cpu/o3/fetch_impl.hh
AgeCommit message (Expand)Author
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-11O3: Add fatal when fetchWidth > Impl::MaxWidth.Brian Grayson
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
2012-02-10O3 Fetch: Check if PC is pointing to Microcode ROMNilay Vaish
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-28Merge with the main repo.Gabe Black
2012-01-17CPU: Moving towards a more general port across CPU modelsAndreas Hansson
2012-01-07Another merge with the main repository.Gabe Black
2011-12-13gcc: fix unused variable warnings from GCC 4.6.1Nathan Binkert
2011-11-18SE/FS: Get rid of FULL_SYSTEM in the CPU directory.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-08-14O3: When squashing, restore the macroop that should be used for fetching.Gabe Black
2011-08-14O3: Add a pointer to the macroop for a microop in the dyninst.Gabe Black
2011-08-13O3: At the end of an instruction, force fetchAddr to something sensible.Gabe Black
2011-08-09O3: Stop using the current macroop no matter why you're leaving it.Gabe Black
2011-07-30O3: Fix corner case squashing into the microcode ROM.Gabe Black
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
2011-07-10O3: Fix up pipelining icache accesses in fetch stage to function properlyGeoffrey Blake
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-06-10o3: missing newlines on some dprintfsKorey Sewell
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-25O3CPU: Fix iqCount and lsqCount SMT fetch policies.Timothy M. Jones
2011-02-23O3: Fix bug when a squash occurs right before TLB miss returns.Ali Saidi
2011-02-13O3: Fetch from the microcode ROM when needed.Gabe Black
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
2011-02-02O3: Fix a style bug in O3.Gabe Black
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18O3: Fix mispredicts from non control instructions.Matt Horsnell
2011-01-18O3: Support timing translations for O3 CPU fetch.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
2010-08-23ARM: Improve printing of uop disassembly.Min Kyu Jeong
2009-09-26O3: Mark fetch stage as active if it faults.Steve Reinhardt
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt