gem5 - gem5

Age	Commit message (Expand)	Author
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu/o3: clean up rename map and free list	Steve Reinhardt
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2008-02-27	Add comments in code to describe bug conditions.	Korey Sewell
2008-02-27	Fix offset in removeThread() function so that float registers start freeing up	Korey Sewell
2007-04-22	Make the floating point zero register special handling only apply for ALPHA.	Gabe Black
2006-06-02	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2006-06-02	Fixes to get compiling to work. This is mainly fixing up some includes; chan...	Kevin Lim
2006-05-31	Updated Authors from bk prs info	Ali Saidi
2006-05-30	Merge ktlim@zizzer:/bk/m5	Kevin Lim
2006-05-22	New directory structure:	Steve Reinhardt