gem5 - gem5

Age	Commit message (Expand)	Author
2015-09-15	cpu, o3: consider split requests for LSQ checksnoop operations	Hongil Yoon
2015-05-05	mem, cpu: Add a separate flag for strictly ordered memory	Andreas Sandberg
2015-03-09	cpu: o3: Remove unused code in iew, add assert instead.	Nilay Vaish
2014-10-29	cpu: Add drain check functionality to IEW	Mitch Hayenga
2014-09-03	cpu: Fix cache blocked load behavior in o3 cpu	Mitch Hayenga
2014-09-03	cpu: Fix o3 front-end pipeline interlock behavior	Mitch Hayenga
2014-09-03	cpu: Change writeback modeling for outstanding instructions	Mitch Hayenga
2014-06-21	o3: make dispatch LSQ full check more selective	Binh Pham
2014-06-21	o3: split load & store queue full cases in rename	Binh Pham
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
2014-04-23	cpu: Add O3 CPU width checks	Dam Sunwoo
2014-04-19	o3: Fix occupancy checks for SMT	Faissal Sleiman
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-10-17	cpu: Change IEW DPRINTF to use IEW debug flag	Faissal Sleiman
2013-06-27	cpu: Consider instructions waiting for FU completion in draining	Andreas Hansson
2013-02-15	o3: fix tick used for renaming and issue with range selection	Matt Horsnell
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	cpu: Initialize the O3 pipeline from startup()	Andreas Sandberg
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-03-09	O3/Ozone: Eliminate dead code counting software prefetch insts	Geoffrey Blake
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-10	DPRINTF: Improve some dprintf messages.	Nilay Vaish
2011-08-19	O3: Squash the violator and younger instructions instead not all insts.	Giacomo Gabrielli
2011-07-15	O3: Create a pipeline activity viewer for the O3 CPU model.	Giacomo Gabrielli
2011-05-23	O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.	Geoffrey Blake
2011-05-13	O3: Fix an issue with a load & branch instruction and mem dep squashing	Geoffrey Blake
2011-04-19	stats: rename stats so they can be used as python expressions	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: fix up code after sorting	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-17	O3: Cleanup the commitInfo comm struct.	Ali Saidi
2011-02-23	O3: When a prefetch causes a fault, don't record it in the inst	Ali Saidi
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2011-02-06	mcpat: Adds McPAT performance counters	Joel Hestness
2011-01-18	O3: Don't test misprediction on load instructions until executed.	Matt Horsnell
2011-01-18	O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.	Matt Horsnell
2011-01-18	O3: Fix mispredicts from non control instructions.	Matt Horsnell
2011-01-18	O3: Fixes the way prefetches are handled inside the iew unit.	Matt Horsnell
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2011-01-18	O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.	Min Kyu Jeong
2011-01-03	Move sched_list.hh and timebuf.hh from src/base to src/cpu.	Steve Reinhardt
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-23	O3: Skipping mem-order violation check for uncachable loads.	Min Kyu Jeong
2010-08-23	ARM: mark msr/mrs instructions as SerializeBefore/After	Min Kyu Jeong
2010-08-23	O3: Handle loads when the destination is the PC.	Min Kyu Jeong