index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
o3
/
inst_queue_impl.hh
Age
Commit message (
Expand
)
Author
2018-11-16
cpu: Fix the usage of const DynInstPtr
Rekai Gonzalez-Alberquilla
2018-07-24
cpu-o3: Missing freeing the heads of DepGraph in IQ squashing
Hanhwi Jang
2017-11-28
cpu-o3: Add missing vector stat initializers
Andreas Sandberg
2017-07-05
arch: ISA parser additions of vector registers
Rekai Gonzalez-Alberquilla
2017-07-05
cpu: Added interface for vector reg file
Rekai Gonzalez-Alberquilla
2017-07-05
cpu: Simplify the rename interface and use RegId
Rekai Gonzalez-Alberquilla
2017-07-05
cpu: Physical register structural + flat indexing
Nathanael Premillieu
2015-05-05
cpu: Change literal integer constants to meaningful labels
Rekai Gonzalez Alberquilla
2016-02-06
style: fix missing spaces in control statements
Steve Reinhardt
2015-07-28
revert 5af8f40d8f2c
Nilay Vaish
2015-07-26
cpu: implements vector registers
Nilay Vaish
2015-04-29
cpu: o3: replace issueLatency with bool pipelined
Nilay Vaish
2015-04-22
cpu: remove conditional check (count > 0) on o3 IQ squashes
Brandon Potter
2014-10-29
cpu: Add writeback modeling for drain functionality
Mitch Hayenga
2014-10-29
cpu: Add drain check functionality to IEW
Mitch Hayenga
2014-09-03
cpu: Fix cache blocked load behavior in o3 cpu
Mitch Hayenga
2014-09-03
cpu: Change writeback modeling for outstanding instructions
Mitch Hayenga
2014-05-31
style: eliminate equality tests with true and false
Steve Reinhardt
2014-01-24
cpu: Add support for Memory+Barrier instruction types in O3 cpu.
Giacomo Gabrielli
2014-01-24
cpu: Relax check on squashed non-speculative instructions
Andreas Hansson
2013-10-17
cpu: add consistent guarding to *_impl.hh files.
Matt Horsnell
2013-10-15
cpu: add a condition-code register class
Yasuko Eckert
2013-01-07
cpu: Rewrite O3 draining to avoid stopping in microcode
Andreas Sandberg
2012-09-07
Param: Transition to Cycles for relevant parameters
Andreas Hansson
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-08-28
Clock: Rework clocks to avoid tick-to-cycle transformations
Andreas Hansson
2012-06-05
O3: Clean up the O3 structures and try to pack them a bit better.
Ali Saidi
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2011-09-22
event: minor cleanup
Steve Reinhardt
2011-08-07
O3: Let squashed and deferred instructions issue.
Gabe Black
2011-07-15
O3: Create a pipeline activity viewer for the O3 CPU model.
Giacomo Gabrielli
2011-05-04
O3: Remove assertion for case that is actually handled in code.
Ali Saidi
2011-04-19
stats: rename stats so they can be used as python expressions
Nathan Binkert
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-02-23
O3: If there is an outstanding table walk don't let the inst queue sleep.
Ali Saidi
2011-02-13
O3: Fix GCC 4.2.4 complaint
Ali Saidi
2011-02-11
O3: Enhance data address translation by supporting hardware page table walkers.
Giacomo Gabrielli
2011-02-06
mcpat: Adds McPAT performance counters
Joel Hestness
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-10-31
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
Gabe Black
2010-08-23
ARM: mark msr/mrs instructions as SerializeBefore/After
Min Kyu Jeong
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
2008-08-11
params: Convert the CPU objects to use the auto generated param structs.
Nathan Binkert
2008-02-06
Make the Event::description() a const function
Stephen Hines
2008-01-14
The reason is that the event is supposed to put the instructions ready to exe...
Ke Meng
2007-09-28
Rename cycles() function to ticks()
Ali Saidi
2007-07-26
Merge python and x86 changes with cache branch
Nathan Binkert
2007-07-23
Major changes to how SimObjects are created and initialized. Almost all
Nathan Binkert
2007-06-30
Event descriptions should not end in "event"
Steve Reinhardt
[next]