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gem5
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invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
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src
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cpu
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o3
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inst_queue_impl.hh
Age
Commit message (
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)
Author
2011-02-11
O3: Enhance data address translation by supporting hardware page table walkers.
Giacomo Gabrielli
2011-02-06
mcpat: Adds McPAT performance counters
Joel Hestness
2011-01-07
Replace curTick global variable with accessor functions.
Steve Reinhardt
2010-10-31
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
Gabe Black
2010-08-23
ARM: mark msr/mrs instructions as SerializeBefore/After
Min Kyu Jeong
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
2008-08-11
params: Convert the CPU objects to use the auto generated param structs.
Nathan Binkert
2008-02-06
Make the Event::description() a const function
Stephen Hines
2008-01-14
The reason is that the event is supposed to put the instructions ready to exe...
Ke Meng
2007-09-28
Rename cycles() function to ticks()
Ali Saidi
2007-07-26
Merge python and x86 changes with cache branch
Nathan Binkert
2007-07-23
Major changes to how SimObjects are created and initialized. Almost all
Nathan Binkert
2007-06-30
Event descriptions should not end in "event"
Steve Reinhardt
2007-04-13
Remove most of the special handling for delay slots since they have to be squ...
Gabe Black
2007-04-04
Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...
Kevin Lim
2007-04-02
Remove/comment out DPRINTFs that were causing a segfault.
Kevin Lim
2007-03-23
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2007-03-23
Handle status bits a little better, as well as non-speculative instructions.
Kevin Lim
2007-03-06
Move all of the parameters of the Root SimObject so they are
Nathan Binkert
2006-12-20
don't use (*activeThreads).begin(), use activeThreads->blah().
Nathan Binkert
2006-09-30
Merge ktlim@zamp:./local/clean/o3-merge/m5
Kevin Lim
2006-08-31
add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throug...
Korey Sewell
2006-08-15
Cleaned up include files and got rid of many using directives in header files.
Gabe Black
2006-07-23
This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...
Korey Sewell
2006-07-05
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-07-05
Add some different parameters. The main change is that the writeback count i...
Kevin Lim
2006-07-02
Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)
Korey Sewell
2006-06-14
Minor code cleanup of BaseDynInst.
Kevin Lim
2006-06-13
Minor updates for stats.
Kevin Lim
2006-06-09
Removing of old code and adding in new comments.
Kevin Lim
2006-06-04
Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
Kevin Lim
2006-06-02
Merge ktlim@zizzer:/bk/newmem
Kevin Lim
2006-06-02
Fixes to get compiling to work. This is mainly fixing up some includes; chan...
Kevin Lim
2006-05-31
Updated Authors from bk prs info
Ali Saidi
2006-05-30
Merge ktlim@zizzer:/bk/m5
Kevin Lim
2006-05-22
New directory structure:
Steve Reinhardt