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path: root/src/cpu/o3/inst_queue_impl.hh
AgeCommit message (Expand)Author
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2011-09-22event: minor cleanupSteve Reinhardt
2011-08-07O3: Let squashed and deferred instructions issue.Gabe Black
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
2011-05-04O3: Remove assertion for case that is actually handled in code.Ali Saidi
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-02-23O3: If there is an outstanding table walk don't let the inst queue sleep.Ali Saidi
2011-02-13O3: Fix GCC 4.2.4 complaintAli Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-02-06Make the Event::description() a const functionStephen Hines
2008-01-14The reason is that the event is supposed to put the instructions ready to exe...Ke Meng
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-04-13Remove most of the special handling for delay slots since they have to be squ...Gabe Black
2007-04-04Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...Kevin Lim
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Handle status bits a little better, as well as non-speculative instructions.Kevin Lim
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-08-31add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throug...Korey Sewell
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-07-05Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-05Add some different parameters. The main change is that the writeback count i...Kevin Lim
2006-07-02Fix default SMT configuration in O3CPU (i.e. fetch policy, workloads/numThreads)Korey Sewell
2006-06-14Minor code cleanup of BaseDynInst.Kevin Lim
2006-06-13Minor updates for stats.Kevin Lim
2006-06-09Removing of old code and adding in new comments.Kevin Lim
2006-06-04Merge ktlim@zamp:/z/ktlim2/clean/m5-o3Kevin Lim
2006-06-02Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-06-02Fixes to get compiling to work. This is mainly fixing up some includes; chan...Kevin Lim
2006-05-31Updated Authors from bk prs infoAli Saidi
2006-05-30Merge ktlim@zizzer:/bk/m5Kevin Lim
2006-05-22New directory structure:Steve Reinhardt
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