summaryrefslogtreecommitdiff
path: root/src/cpu/o3/inst_queue_impl.hh
AgeCommit message (Expand)Author
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
2017-11-28cpu-o3: Add missing vector stat initializersAndreas Sandberg
2017-07-05arch: ISA parser additions of vector registersRekai Gonzalez-Alberquilla
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
2017-07-05cpu: Physical register structural + flat indexingNathanael Premillieu
2015-05-05cpu: Change literal integer constants to meaningful labelsRekai Gonzalez Alberquilla
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-04-29cpu: o3: replace issueLatency with bool pipelinedNilay Vaish
2015-04-22cpu: remove conditional check (count > 0) on o3 IQ squashesBrandon Potter
2014-10-29cpu: Add writeback modeling for drain functionalityMitch Hayenga
2014-10-29cpu: Add drain check functionality to IEWMitch Hayenga
2014-09-03cpu: Fix cache blocked load behavior in o3 cpuMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Relax check on squashed non-speculative instructionsAndreas Hansson
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2011-09-22event: minor cleanupSteve Reinhardt
2011-08-07O3: Let squashed and deferred instructions issue.Gabe Black
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
2011-05-04O3: Remove assertion for case that is actually handled in code.Ali Saidi
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-02-23O3: If there is an outstanding table walk don't let the inst queue sleep.Ali Saidi
2011-02-13O3: Fix GCC 4.2.4 complaintAli Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-23ARM: mark msr/mrs instructions as SerializeBefore/AfterMin Kyu Jeong
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-02-06Make the Event::description() a const functionStephen Hines
2008-01-14The reason is that the event is supposed to put the instructions ready to exe...Ke Meng
2007-09-28Rename cycles() function to ticks()Ali Saidi
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-04-13Remove most of the special handling for delay slots since they have to be squ...Gabe Black