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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
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tree
commit
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path:
root
/
src
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cpu
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o3
/
lsq.hh
Age
Commit message (
Expand
)
Author
2016-04-07
mem: Remove threadId from memory request class
Mitch Hayenga
2016-04-06
Revert power patch sets with unexpected interactions
Andreas Sandberg
2016-04-05
mem: Remove threadId from memory request class
Mitch Hayenga
2016-01-17
cpu: remove unnecessary data ptr from O3 internal read() funcs
Steve Reinhardt
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2014-09-03
cpu: Fix cache blocked load behavior in o3 cpu
Mitch Hayenga
2014-06-21
o3: split load & store queue full cases in rename
Binh Pham
2013-09-11
cpu: Dynamically instantiate O3 CPU LSQUnits
Joel Hestness
2013-01-07
cpu: Rewrite O3 draining to avoid stopping in microcode
Andreas Sandberg
2013-01-07
cpu: Fix O3 LSQ debug dumping constness and formatting
Andreas Sandberg
2012-12-06
o3 cpu: remove some unused buggy functions in the lsq
Nathanael Premillieu
2012-05-01
MEM: Separate requests and responses for timing accesses
Andreas Hansson
2012-04-14
MEM: Separate snoops and normal memory requests/responses
Andreas Hansson
2012-01-31
Merge with head, hopefully the last time for this batch.
Gabe Black
2012-01-31
clang: Enable compiling gem5 using clang 2.9 and 3.0
Koan-Sin Tan
2012-01-28
Merge with the main repo.
Gabe Black
2012-01-17
CPU: Moving towards a more general port across CPU models
Andreas Hansson
2012-01-17
MEM: Add port proxies instead of non-structural ports
Andreas Hansson
2011-11-18
SE/FS: Get rid of includes of config/full_system.hh.
Gabe Black
2011-11-18
SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
Gabe Black
2011-04-15
includes: sort all includes
Nathan Binkert
2010-08-13
CPU: Add readBytes and writeBytes functions to the exec contexts.
Gabe Black
2010-02-12
O3PCU: Split loads and stores that cross cache line boundaries.
Timothy M. Jones
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2008-11-02
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
Lisa Hsu
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
2008-08-11
params: Convert the CPU objects to use the auto generated param structs.
Nathan Binkert
2008-06-28
Backed out changeset 94a7bb476fca: caused memory leak.
Steve Reinhardt
2008-06-21
Generate more useful error messages for unconnected ports.
Steve Reinhardt
2007-05-21
Change getDeviceAddressRanges to use bool for snoop arg.
Steve Reinhardt
2007-04-04
Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...
Kevin Lim
2007-03-09
Two fixes:
Kevin Lim
2006-12-15
little fixes i noticed while searching for reason for address range issues (b...
Lisa Hsu
2006-11-13
Make CPU models signal to update the snoop ranges
Ron Dreslinski
2006-10-09
Have cpus send snoop ranges
Ron Dreslinski
2006-07-13
Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...
Kevin Lim
2006-07-07
Support Ron's changes for hooking up ports.
Kevin Lim
2006-06-16
Two updates that got combined into one ChangeSet accidentally. They're both ...
Kevin Lim
2006-06-13
Minor updates for stats.
Kevin Lim
2006-06-09
Removing of old code and adding in new comments.
Kevin Lim
2006-06-07
Update copyright.
Kevin Lim
2006-06-04
Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
Kevin Lim
2006-06-02
Fixes to get compiling to work. This is mainly fixing up some includes; chan...
Kevin Lim
