gem5 - gem5

Age	Commit message (Expand)	Author
2019-05-12	only spec load when hit	Iru Cai
2019-03-20	invisispec-1.0 source	Iru Cai
2018-12-03	cpu: Change raw pointers to STL Containers	Rekai Gonzalez-Alberquilla
2018-11-27	arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.	Gabe Black
2018-11-16	cpu: Fix the usage of const DynInstPtr	Rekai Gonzalez-Alberquilla
2018-06-11	misc: Using smart pointers for memory Requests	Giacomo Travaglini
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2014-12-02	cpu, o3: Ignored invalidate causing same-address load reordering	Marco Elver
2014-12-02	cpu: Move packet deallocation to recvTimingResp in the O3 CPU	Stephan Diestelhorst
2014-09-03	cpu: Fix cache blocked load behavior in o3 cpu	Mitch Hayenga
2014-06-21	o3: split load & store queue full cases in rename	Binh Pham
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-09-11	cpu: Dynamically instantiate O3 CPU LSQUnits	Joel Hestness
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	cpu: Fix O3 LSQ debug dumping constness and formatting	Andreas Sandberg
2012-12-06	o3 cpu: remove some unused buggy functions in the lsq	Nathanael Premillieu
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-06-10	o3: missing newlines on some dprintfs	Korey Sewell
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-09-26	O3CPU: Fix thread writeback logic.	Kevin Lim
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-06-28	Backed out changeset 94a7bb476fca: caused memory leak.	Steve Reinhardt
2008-06-21	Generate more useful error messages for unconnected ports.	Steve Reinhardt
2007-08-26	Merge with head	Gabe Black
2007-08-21	o3: Fix for retry ID bug.	Kevin Lim
2007-07-15	Fix up a bunch of multilevel coherence issues.	Steve Reinhardt
2007-04-04	Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...	Kevin Lim
2007-04-02	Remove/comment out DPRINTFs that were causing a segfault.	Kevin Lim
2007-03-09	Two fixes:	Kevin Lim
2006-12-21	style	Nathan Binkert
2006-12-20	don't use (*activeThreads).begin(), use activeThreads->blah().	Nathan Binkert
2006-11-13	Make CPU models signal to update the snoop ranges	Ron Dreslinski
2006-11-13	Change warn to DPRINTF.	Kevin Lim
2006-10-19	Small changes:	Ron Dreslinski
2006-10-17	Fixes for uni-coherence in timing mode for FS.	Ron Dreslinski
2006-10-08	Fixes for functional path.	Ron Dreslinski
2006-10-02	Updates to fix merge issues and bring almost everything up to working speed. ...	Kevin Lim
2006-09-30	Merge ktlim@zamp:./local/clean/o3-merge/m5	Kevin Lim
2006-08-16	Fixes for Kevins O3 model to work with the blocking caches.	Ron Dreslinski