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gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
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path:
root
/
src
/
cpu
/
o3
/
lsq_unit.hh
Age
Commit message (
Expand
)
Author
2006-08-16
Fixes for Kevins O3 model to work with the blocking caches.
Ron Dreslinski
2006-07-19
O3CPU fixes.
Kevin Lim
2006-07-13
Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...
Kevin Lim
2006-07-07
Support Ron's changes for hooking up ports.
Kevin Lim
2006-06-27
Make full CPU handle SE faults
Ali Saidi
2006-06-22
Misc fixes.
Kevin Lim
2006-06-16
Two updates that got combined into one ChangeSet accidentally. They're both ...
Kevin Lim
2006-06-14
Minor code cleanup of BaseDynInst.
Kevin Lim
2006-06-13
Minor updates for stats.
Kevin Lim
2006-06-09
Removing of old code and adding in new comments.
Kevin Lim
2006-06-09
Fixes for some outstanding issues in the LSQ. It should now be able to retry...
Kevin Lim
2006-06-07
Update copyright.
Kevin Lim
2006-06-05
Fixes to get new CPU model working for simple test case. The CPU does not ye...
Kevin Lim
2006-06-04
Merge ktlim@zamp:/z/ktlim2/clean/m5-o3
Kevin Lim
2006-06-02
Fixes to get compiling to work. This is mainly fixing up some includes; chan...
Kevin Lim
