gem5 - gem5

Age	Commit message (Expand)	Author
2012-12-06	o3 cpu: remove some unused buggy functions in the lsq	Nathanael Premillieu
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-02-07	Faults: Turn off arch/faults.hh	Gabe Black
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-28	O3 CPU LSQ: Implement TSO	Nilay Vaish
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-09-27	Faults: Replace calls to genMachineCheckFault with M5PanicFault.	Gabe Black
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-08-16	O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.	Gabe Black
2011-07-31	O3: Implement memory mapped IPRs for O3.	Gabe Black
2011-05-23	O3: Fix offset calculation into storeQueue buffer for store->load forwarding	Geoffrey Blake
2011-05-23	O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.	Geoffrey Blake
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: fix up code after sorting	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-04	O3: Tighten memory order violation checking to 16 bytes.	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-12-07	O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-23	O3: Handle loads when the destination is the PC.	Min Kyu Jeong
2010-08-13	CPU: Add readBytes and writeBytes functions to the exec contexts.	Gabe Black
2010-07-22	LSQ Unit: After deleting part of a split request, set it to NULL so that it	Timothy M. Jones
2010-07-22	O3CPU: Fix a bug where stores in the cpu where never marked as split.	Timothy M. Jones
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2009-03-05	stats: Fix all stats usages to deal with template fixes	Nathan Binkert
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-03-24	Don't FastAlloc MSHRs since we don't allocate them on the fly.	Steve Reinhardt
2008-02-06	Make the Event::description() a const function	Stephen Hines
2007-06-30	Make CPU models use new LoadLockedReq/StoreCondReq commands.	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt
2007-04-21	fixes for solaris compile	Ali Saidi
2007-04-04	Merge zizzer.eecs.umich.edu:/bk/newmem	Gabe Black
2007-04-04	Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...	Kevin Lim
2007-04-03	Made the "data" field of store queue entries into a character array. It's siz...	Gabe Black
2007-03-23	Merge ktlim@zizzer:/bk/newmem	Kevin Lim
2007-03-23	Two fixes:	Kevin Lim