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path: root/src/cpu/o3/lsq_unit_impl.hh
AgeCommit message (Expand)Author
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2014-12-02cpu, o3: Ignored invalidate causing same-address load reorderingMarco Elver
2014-12-02cpu: Move packet deallocation to recvTimingResp in the O3 CPUStephan Diestelhorst
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-09-20base: Clean up redundant string functions and use C++11Andreas Hansson
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03cpu: Fix cache blocked load behavior in o3 cpuMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17cpu: Put in assertions to check for maximum supported LQ/SQ sizeFaissal Sleiman
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2013-01-07cpu: Fix O3 LSQ debug dumping constness and formattingAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-28O3 CPU LSQ: Implement TSONilay Vaish
2011-09-27O3: Tidy up some DPRINTFs in the LSQ.Gabe Black
2011-09-27Faults: Replace calls to genMachineCheckFault with M5PanicFault.Gabe Black
2011-09-26LSQ: Moved a couple of lines to enable O3 + RubyNilay Vaish
2011-09-22event: minor cleanupSteve Reinhardt
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
2011-07-31O3: Implement memory mapped IPRs for O3.Gabe Black
2011-05-04O3: Fix a small corner case with the lsq hazard detection logic.Ali Saidi
2011-04-20stats: one more name violationNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-01-18O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.Matt Horsnell
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black