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path: root/src/cpu/o3/lsq_unit_impl.hh
AgeCommit message (Expand)Author
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory instru...Min Kyu Jeong
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-02-06Make the Event::description() a const functionStephen Hines
2007-08-26Merge with headGabe Black
2007-08-21o3: Fix for retry ID bug.Kevin Lim
2007-07-23Fix WriteReq/StoreCondReq setting in O3.Steve Reinhardt
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-04-26Remove extra delete that was causing segfault.Kevin Lim
2007-04-08Get the "hard" SPARC instructions working in o3. I don't like that the IsStor...Gabe Black
2007-04-04Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-04-04Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...Kevin Lim
2007-04-03Made the "data" field of store queue entries into a character array. It's siz...Gabe Black
2007-04-03Fix a memory leak. Hopefully this fixes the longer running benchmarks.Kevin Lim
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Two fixes:Kevin Lim
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2006-12-16Make sure endian conversion is done on the memory data when it's just set to ...Gabe Black
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
2006-12-11Fix up in case a req hasn't yet been generated for this instruction (if there...Kevin Lim
2006-12-06Added in endianness conversion on memory accesses as the data goes out. This ...Gabe Black
2006-11-10Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-11-05Initialize pointer to NULL.Kevin Lim
2006-10-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-23Add in support for LL/SC in the O3 CPU. Needs to be fully tested.Kevin Lim
2006-10-20Use PacketPtr everywhereNathan Binkert
2006-10-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
2006-10-08Updates to O3 CPU. It should now work in FS mode, although sampling still ha...Kevin Lim
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-08-16Fixes for Kevins O3 model to work with the blocking caches.Ron Dreslinski
2006-07-19O3CPU fixes.Kevin Lim
2006-07-13Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...Kevin Lim
2006-07-07Support Ron's changes for hooking up ports.Kevin Lim
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