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path: root/src/cpu/o3/lsq_unit_impl.hh
AgeCommit message (Expand)Author
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2013-01-07cpu: Fix O3 LSQ debug dumping constness and formattingAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-28O3 CPU LSQ: Implement TSONilay Vaish
2011-09-27O3: Tidy up some DPRINTFs in the LSQ.Gabe Black
2011-09-27Faults: Replace calls to genMachineCheckFault with M5PanicFault.Gabe Black
2011-09-26LSQ: Moved a couple of lines to enable O3 + RubyNilay Vaish
2011-09-22event: minor cleanupSteve Reinhardt
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
2011-07-31O3: Implement memory mapped IPRs for O3.Gabe Black
2011-05-04O3: Fix a small corner case with the lsq hazard detection logic.Ali Saidi
2011-04-20stats: one more name violationNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-01-18O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.Matt Horsnell
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-08-23O3: Skipping mem-order violation check for uncachable loads.Min Kyu Jeong
2010-08-23CPU: Make Exec trace to print predication result (if false) for memory instru...Min Kyu Jeong
2010-08-23O3: Handle loads when the destination is the PC.Min Kyu Jeong
2010-08-23ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.Min Kyu Jeong
2010-02-12O3PCU: Split loads and stores that cross cache line boundaries.Timothy M. Jones
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-08-11params: Convert the CPU objects to use the auto generated param structs.Nathan Binkert
2008-02-06Make the Event::description() a const functionStephen Hines
2007-08-26Merge with headGabe Black
2007-08-21o3: Fix for retry ID bug.Kevin Lim
2007-07-23Fix WriteReq/StoreCondReq setting in O3.Steve Reinhardt
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt