gem5 - gem5

Age	Commit message (Expand)	Author
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-02-15	o3: fix tick used for renaming and issue with range selection	Matt Horsnell
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	cpu: Fix O3 LSQ debug dumping constness and formatting	Andreas Sandberg
2013-01-07	o3: Fix issue with LLSC ordering and speculation	Ali Saidi
2012-12-06	o3 cpu: remove some unused buggy functions in the lsq	Nathanael Premillieu
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-28	O3 CPU LSQ: Implement TSO	Nilay Vaish
2011-09-27	O3: Tidy up some DPRINTFs in the LSQ.	Gabe Black
2011-09-27	Faults: Replace calls to genMachineCheckFault with M5PanicFault.	Gabe Black
2011-09-26	LSQ: Moved a couple of lines to enable O3 + Ruby	Nilay Vaish
2011-09-22	event: minor cleanup	Steve Reinhardt
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-07-31	O3: Implement memory mapped IPRs for O3.	Gabe Black
2011-05-04	O3: Fix a small corner case with the lsq hazard detection logic.	Ali Saidi
2011-04-20	stats: one more name violation	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-04	O3: Tighten memory order violation checking to 16 bytes.	Ali Saidi
2011-03-17	O3: Fix unaligned stores when cache blocked	Ali Saidi
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2011-01-18	O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.	Matt Horsnell
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-08-23	O3: Skipping mem-order violation check for uncachable loads.	Min Kyu Jeong
2010-08-23	CPU: Make Exec trace to print predication result (if false) for memory instru...	Min Kyu Jeong
2010-08-23	O3: Handle loads when the destination is the PC.	Min Kyu Jeong
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2008-10-09	eventq: convert all usage of events to use the new API.	Nathan Binkert
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-02-06	Make the Event::description() a const function	Stephen Hines
2007-08-26	Merge with head	Gabe Black
2007-08-21	o3: Fix for retry ID bug.	Kevin Lim
2007-07-23	Fix WriteReq/StoreCondReq setting in O3.	Steve Reinhardt
2007-06-30	Make CPU models use new LoadLockedReq/StoreCondReq commands.	Steve Reinhardt
2007-06-30	Event descriptions should not end in "event"	Steve Reinhardt
2007-06-30	Get rid of Packet result field. Error responses are	Steve Reinhardt